Ferroelectric memory and operating method therefor

Details Ferroelectric memory and operating method therefor Ferroelectric memory and operating method therefor

2002-04-18

2004-08-31

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S189110

Reexamination Certificate

active

06785155

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a ferroelectric memory and an operating method therefor, and more particularly, it relates to a ferroelectric memory having ferroelectric capacitors and an operating method therefor.
2. Description of the Prior Art
A ferroelectric memory is recently watched with interest as a high-speed nonvolatile memory requiring low power consumption. Therefore, such a ferroelectric memory is actively subjected to research and development.
FIG. 7
is a representative circuit diagram of a conventional ferroelectric memory most generally in use, and
FIG. 8
is a sectional view corresponding to FIG.
7
. Referring to
FIGS. 7 and 8
, element isolation regions
102
are formed on prescribed areas of the surface of a semiconductor substrate
101
in the conventional structure. Source/drain regions
103
and
104
are formed on an element forming region enclosed with the element isolation regions
102
at prescribed intervals. Gate electrodes
106
forming word lines (WL) are formed on channel regions located between the source/drain regions
103
and
104
through gate insulator films
105
. Bit lines (BL)
113
are electrically connected to the source/drain regions
104
.
The source/drain regions
103
are formed with lower electrodes
109
through plug electrodes
108
. Upper electrodes
111
forming plate lines (PL) are formed on the lower electrodes
109
through ferroelectric films
110
. The lower electrodes
190
, the ferroelectric films
110
and the upper electrodes
111
form ferroelectric capacitors
112
. The source/drain regions
103
and
104
, gate insulator films
105
, and the gate electrodes
106
form transistors
107
. The transistors
107
function as switches for selecting memory cells
100
. As shown in
FIG. 7
, each memory cell
100
is formed by a single transistor
107
and a single ferroelectric capacitor
112
.
In the structure of the conventional ferroelectric memory shown in
FIGS. 7 and 8
, however, each memory cell
100
formed by a single transistor
107
and a single ferroelectric capacitor
112
disadvantageously requires a relatively large memory cell area.
To this end, there have generally been developed a simple matrix ferroelectric memory forming each memory cell only by a single ferroelectric capacitor and an MFIS-FET (metal ferroelectric insulator semiconductor-field effect transistor) ferroelectric memory or an MFMIS-FET (metal ferroelectric metal insulator semiconductor-field effect transistor) ferroelectric memory forming a ferroelectric capacitor on the gate portion of a transistor.
FIG. 9
is a circuit diagram of a conventional simple matrix ferroelectric memory, and
FIG. 10
is a sectional view corresponding to FIG.
9
. Referring to
FIGS. 9 and 10
, ferroelectric layers
202
are formed on bit lines (BL)
201
in the conventional simple matrix ferroelectric memory. Word lines (WL)
203
are formed on the ferroelectric layers
202
in a direction intersecting with the bit lines
201
. The bit lines
201
, the ferroelectric layers
202
and the word lines
203
form ferroelectric capacitors
210
. In this simple matrix ferroelectric memory, each memory cell
200
is formed by only a single ferroelectric capacitor
210
, as shown in FIG.
9
.
FIG. 11
is a circuit diagram for illustrating a method of applying a voltage in the conventional simple matrix ferroelectric memory shown in
FIGS. 9 and 10
in a write operation. Referring to
FIG. 11
, a voltage V
CC
is applied across a bit line BL
1
and a word line WL
1
connected with a selected memory cell (hereinafter referred to as a selected cell)
200
in the conventional simple matrix ferroelectric memory, in order to drive the selected cell
200
. In other words, a power supply voltage V
CC
is applied to the bit line BL
1
while applying 0 V to the word line WL
1
. A voltage 1/3V
CC
is applied to bit lines BL
0
and BL
2
connected with non-selected memory cells (hereinafter referred to as non-selected cells)
200
while applying a voltage 2/3V
CC
is applied to word lines WL
0
and WL
2
connected with the non-selected cells
200
. Thus, the voltage V
CC
is applied to the selected cell
200
while the voltage 1/3V
CC
is applied to the non-selected cells
200
.
In the above case, it is necessary that polarization inversion is sufficiently saturated for the ferroelectric layer
202
of the selected cell
200
while polarization states remain substantially unchanged for the ferroelectric layers
202
of the non-selected cells
200
.
Under the present circumstances, however, the angular shape of ferroelectric hysteresis is so insufficient that information (charge quantity) is lost in the so-called disturbance when the voltage 1/3V
CC
is continuously applied to the non-selected cells
200
in the same direction, as shown in FIG.
12
. When such disturbance is caused, the information written in the non-selected cells
200
is lost to cause difficulty in employment of the ferroelectric memory. At present, therefore, it is considered difficult to put the ferroelectric memory having the simple matrix structure shown in
FIGS. 9 and 10
into practice.
FIG. 13
is a circuit diagram showing a conventional one-transistor ferroelectric memory having memory cells formed by MFMIS-FETs, and
FIG. 14
is a sectional view corresponding to FIG.
13
. Referring to
FIGS. 13 and 14
, a well region
302
is formed on the surface of a semiconductor substrate
301
in this one-transistor ferroelectric memory. Source/drain regions
303
and
304
are formed on the surface of the well region
302
at prescribed intervals. Gate electrodes
306
are formed on channel regions located between the source/drain regions
303
and
304
through gate insulator films
305
.
Word lines (WL)
308
are formed on the gate electrodes
306
through ferroelectric layers
307
. Bit lines (BL)
310
are connected to the source/drain regions
304
. Plate lines (PL)
311
are connected to the source/drain regions
303
. Source lines (SL)
312
are connected to the well region
302
. The gate electrodes
306
, the ferroelectric layers
307
and the word lines
308
form ferroelectric capacitors
315
. The source/drain regions
303
and
304
, gate insulator films
305
, and the gate electrodes
306
form transistors
309
. In this case, each memory cell
300
is formed by a single transistor
309
having a single ferroelectric capacitor
315
provided on the gate portion thereof.
FIG. 15
is an equivalent circuit diagram of the one-transistor ferroelectric memory shown in
FIGS. 13 and 14
in writing. When a write operation similar to that in the simple matrix ferroelectric memory shown in
FIG. 11
is performed and a voltage 1/3V
CC
is continuously applied to non-selected cells
300
in the same direction, therefore, information (charge quantity) in the non-selected cells
300
is lost in the so-called disturbance, similarly to the above.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a ferroelectric memory capable of avoiding disturbance in non-selected memory cells.
Another object of the present invention is to put a simple matrix ferroelectric memory into practice by avoiding disturbance in non-selected cells.
Still another object of the present invention is to avoid disturbance in non-selected memory cells in a one-transistor ferroelectric memory.
In order to attain the aforementioned objects, a ferroelectric memory according to a first aspect of the present invention comprises a memory cell array formed by memory cells having ferroelectric capacitors arranged in the form of a matrix and pulse application means for applying pulses having a prescribed pulse width causing sufficient polarization inversion when applying a high voltage to the ferroelectric capacitors while hardly causing polarization inversion when applying a low voltage to the ferroelectric capacitors to the memory cells. The ferroelectric memory applies a pulse of a high voltage having the aforementioned prescribed pulse width to a selected memory cell w

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