Static information storage and retrieval – Systems using particular element – Capacitors
Reexamination Certificate
2001-11-09
2004-08-17
Elms, Richard (Department: 2824)
Static information storage and retrieval
Systems using particular element
Capacitors
C257S296000, C365S185230
Reexamination Certificate
active
06778424
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application claims the benefit of priority under 35 U.S.C. § 119 to Japanese Patent Application Nos. 2001-41828, 2001-191781 and 2001-328204 filed on Feb. 19, 2001, Jun. 25, 2001 and Oct. 25, 2001, respectively, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device which dynamically stores data with a channel body as a storage node.
2. Description of the Related Art
A memory cell of a DRAM generally used as a large capacity RAM is composed of one MOS transistor and one capacitor, and electric charge is stored in the capacitor with using the MOS transistor as a selection switch. Data is read out at the sight of a change in the potential of a bit line by redistributing the electric charge stored in the cell capacitor to the electric charge of the bit line. Accordingly, there is a lower limit to the storage charge amount of the cell capacitor relative to the initial charge amount of the bit line.
In the DRAM, the parasitic capacity of the bit line reduces with scale-down, but since write charge to the cell also reduces with a reduction in power consumption and scale-down, the capacitance of the cell capacitor does not reduce. The capacitance of the capacitor is proportional to its area and the permittivity of a dielectric (a capacitor insulating film) and inversely proportional to the thickness of the capacitor insulating film. When the thickness of the capacitor insulating film is reduced, a tunnel current flows; hence, insulation properties cannot be maintained. For this reason, there is a limit of about 2 nm to the reduction in the thickness of a film, and a lot of time and money are required to look for and develop a dielectric film which has a permittivity higher than the permittivity of a silicon oxide film such as offsets an area reduced in proportion to the square thereof, is stable in terms of structure, fits a silicon CMOS process, and which is very reliable in actual use.
Therefore, from the mid-1980's, a three-dimensional structure such as a stacked cell structure or a trench cell structure has been used for the capacitor of the DRAM. Even in these stacked cell structure and trench cell structure, recently the ratio of a plane size to a three-dimensional depth exceeds 10, resulting in a cigarette shape. Consequently, an etching limit to a silicon substrate in the case of a trench cell, and boring of a contact hole to bring a lower portion of a capacitor structure into contact with an upper portion thereof, filling of a conductor in this contact hole, and uniform covering properties of a dielectric in the case of a stacked cell come into question, and hence it has been said that those structures are unfit for further scale-down to a size under 100 nm.
An attempt to reduce the capacitor in size by using a gain of the MOS has been made from long ago, and this type of cell is called a gain cell. A drain current changes by the potential of a gate or a back gate of a read MOS transistor, and therefore the gain cell is classified broadly into two types, that is, one which uses a gate electrode as a storage node and the other which uses a channel body as a storage node. Examples of the one which uses the gate electrode of the read MOS transistor as the storage node are one composed of three transistors and one capacitor used in a 1 kbit DRAM by Intel Corporation in days of old and another composed of two transistors and one capacitor. As for capacitors, some are formed positively, and the others use a parasitic capacitor. In any case, in these gain cells, the number of devices is two or more, and gates (word lines) and drains (bit lines) are not common but separate for a write operation and a read operation, whereby the number of connections is large, and consequently, these gain cells are unfit for scale-down.
A gain cell of a type configured to use an SOI substrate, store charge with a channel body of a read MOS (sense MOS) as a storage node, and use a back gate bias effect is proposed. For example, the following documents are given.
(1) H. Wann and C. Hu, “A Capacitorless DRAM Cell on SOI Substrate.” IEDM Digest of Technical Papers, pp. 635-638, DEC., 1933
(2) M. R. Tack, et. al, “The Multistable Charge Controlled Memory Effect in SOI MOS Transistors at Low Temperatures,” IEEE Transactions on Electron Devices, vol. no.5, pp. 1371-1382 May 1990.
In the document (1), one gate electrode is provided and hence this cell seemingly has a one transistor structure, but in reality a PMOS transistor region and an NMOS transistor region are provided under the gate, and its size is larger compared with a single one transistor structure. Moreover, it is necessary to write “0” before writing “1”. Also, as for write speed, it is more unfavorable compared with ordinary SRAM and DRAM. In Translated National Publication of Patent Application No. Hei 9-509284 by the same author, an operation example in which it is unnecessary to write “0” before writing “1” is disclosed, but the PMOS transistor region and the NMOS transistor region are similarly provided under the gate.
In the document (
2
), “1” and “0” cannot be simultaneously written in cells sharing a word line, and an erase operation by the use of an SOI substrate becomes necessary. As for write speed, this gain cell is more unfavorable compared with ordinary SRAM and DRAM.
Japanese Patent Laid-open No. Hei 3-171768 discloses a gain cell of a type configured to store charge with a channel body as a storage node and use a back gate bias effect. In this cell, the source/drain on the side where the bit line is not connected need to be isolated in a bit line direction or a word line direction, whereby the cell size is large. Moreover, it is necessary to write “0” before writing “1”, and thus regarding write speed, it is more unfavorable than ordinary SRAM and DRAM.
Japanese Patent Laid-open No. Hei 8-213624 discloses a gain cell of a type configured to store charge with a channel body as a storage node and use the fact that there is difference in parasitic bipolar collector current depending on the potential of the channel body. Also in this gain cell, it is necessary to write “1” before writing “0”, and regarding write speed, it is more unfavorable than ordinary SRAM and DRAM.
As described above, those recently proposed as a new DRAM need a special transistor structure and hence they have a complicated structure. Alternatively, even if they have a relatively simple structure, they have a drawback in controllability, whereby the achievement of high integration and high performance is difficult.
SUMMARY OF THE INVENTION
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor memory device having MIS transistors to constitute memory cells, each of the MIS transistors comprising:
a semiconductor layer;
a source region formed in the semiconductor layer;
a drain region formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state;
a main gate provided between the source region and the drain region to form a channel in the channel body; and
an auxiliary gate provided separately from the main gate to control a potential of the channel body by capacitive coupling, the auxiliary gate being driven in synchronization with the main gate,
wherein the MIS transistor has a first data state in which the channel body is set at a first potential and a second data state in which the channel body is set at a second potential.
According to another aspect of the present invention, a semiconductor memory device having MIS transistors to constitute memory cells, each of the MIS transistors having a first data state and a second data state, the semiconductor memory device, comprising:
a first semiconductor substrate;
auxiliary gates of the MIS transistors formed on the first semiconductor substrate to c
Iwata Yoshihisa
Ohsawa Takashi
Yamada Takashi
Banner & Witcoff , Ltd.
Elms Richard
Kabushiki Kaisha Toshiba
Nguyen Nam
LandOfFree
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