Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2003-06-13
2004-11-09
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
06815973
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to wafer level testing of integrated circuits.
BACKGROUND INFORMATION
In the manufacture of integrated circuits, each one of many integrated circuits on a wafer is typically tested in what is called wafer-level testing. A probe card having a set of probe needles is made such that the pattern of probe needles on the card corresponds with a pattern of wire bond pads on the face side of each integrated circuit on the wafer. The probe card fits into a piece of probe equipment. The probe equipment brings the probe card down into contact with the wafer such that the probe needles of the probe card come into contact with the corresponding bond pads of one of the integrated circuits on the wafer. Power is typically supplied to the integrated circuit via certain of the probe needles that make contact with the power and ground bond pads of the integrated circuit. The remaining probe needles are used to supply test signals to the integrated circuit and to read back test information from the integrated circuit. Once the test information is read back, the testing of the integrated circuit is complete. The test may, for example, indicate that the integrated circuit is defective or that the integrated circuit functioned correctly.
The probe equipment then lifts the probe card up from the integrated circuit and moves the probe card over to the next integrated circuit on the wafer. The process is then repeated such that the second integrated circuit is tested. In this manner, the integrated circuits of the wafer are tested one by one, row by row.
After all the integrated circuits on the wafer have been tested in this manner, the wafer is typically cut along vertically extending and horizontally extending scribe lines so that each individual integrated circuit becomes a separate integrated circuit die. Each good die is then packaged.
Although integrated circuits are generally powered during wafer-level test via probe card needles as described above, special power and ground lines are sometimes provided on the wafer so that power and ground voltages do not need to be provided by probe card needles. Power and ground conductors may, for example, be provided on the wafer to extend between the various integrated circuits of the wafer in the scribe line areas. The scribe line areas between rows of integrated circuits and between columns of integrated circuits are sometimes called scribe streets.
U.S. Pat. No. 6,323,639, for example, describes powering integrated circuits on a wafer using metal lines disposed in wafer scribe line areas. Each integrated circuit has a first pad for receiving a power supply voltage from one such metal line and a second pad for receiving a ground potential from a second such metal line. The probe card does not, therefore, have to contact the power and ground wire bond pads of the various integrated circuits. Rather, power and ground are supplied through the metal lines. To initiate a built-in self-test (BIST) in the integrated circuit, probe needles of the probe card are brought down into contact with bond pads of a first integrated circuit. These bond pads may, for example, receive test information onto the integrated circuit. Once the built-in self-test operation is properly initiated, the probe card moves to the next integrated circuit. The patent describes a method whereby the end of the testing of one integrated circuit overlaps the start of testing of a second integrated circuit. Test results are stored in a non-volatile status register on the wafer. Upon completion of the built-in self-test operation for all the integrated circuits on the wafer, the results of the testing is evaluated. See U.S. Pat. No. 6,232,639 for more details.
Although some problems associated with supplying power and ground to an integrated circuit using probe needles are avoided using techniques set forth in U.S. Pat. No. 6,323,639, certain other problems still remain. The testing of integrated circuits is, for example, still largely sequential. The testing of a wafer involving a large number of integrated circuits is still undesirably slow. Moreover, the needles of the probe card still make landings on integrated circuit bond pads. Probe needles can fail. Probe cards are expensive. A solution to these problems is desired.
In addition to the above-described problems associated with probe cards, the use of probe cards requires that the integrated circuit being tested have pads to which the probe needles can make contact. More and more integrated circuits are, however, being designed to employ flip-chip packaging techniques. In flip-chip packaging, bond pads are not needed to connect the various input/output resources of the integrated circuit die to the package. Rather than using bond wires and bond pads to couple an integrated circuit to its package, microbump structures are provided on the face side of the integrated circuit. To package the integrated circuit, the integrated circuit is flipped upside down such that the microbumps on the face side of the integrated circuit make electrical contact with a corresponding set of landing pads on the integrated circuit package. Bond wires are not used and the microbumps can be made to be quite small. Because the larger bond pads that were used for wire bonding are not required, it is desirable not to have to provide bond pad structures just to support the needs of probe card wafer testing. Accordingly, a rapid and inexpensive wafer testing technique that does not involve the probing of integrated circuits using a probe card and probe needles is desired.
SUMMARY
A wafer of integrated circuits under test (ICUT) is tested by supplying power to the ICUTs using power and ground traces that extend between rows of the ICUTs in scribe streets. Test information is supplied to each of the powered ICUTs by transmitting the test information optically onto a plurality of ICUTs or onto the entire wafer. Each ICUT includes one or more photodetectors usable for receiving the test information. The photodetectors may, for example, be diodes. In one embodiment, all the ICUTs on the wafer receive the test information at the same time. Each ICUT then uses the test information to perform a self-test. The test information may, for example, include JTAG test input signals (TCK, TMS and TDI).
In addition to photodetectors, each ICUT also has a phototransmitter. The phototransmitter is used for transmitting test information optically from the ICUT. The phototransmitter may, for example, be a diode. In one embodiment, all the many ICUTs on the wafer transmit test results optically at the same time. Each ICUT may, for example, include an optical JTAG port and may transmit the results of a self-test optically in the form of the JTAG TDO output test signal.
Light of the optical test information transmitted from all the ICUTs under test is received by an optical sensing device. In one embodiment, the optical sensing device is a CCD camera. An image of the wafer under test is formed on an array of CCD devices in the camera. Light from the various ICUTs appears as specs in the image. The CCD camera discriminates the various optical test signals, one from another, and outputs test information for each of the ICUTs. The resulting test information is then analyzed to determine which of the ICUTs passed self-test and which of the ICUTs failed self-test. An entire wafer of ICUTs is therefore tested simultaneously. If powering an entire wafer of ICUTs requires an excessive amount of power and leads to heat dissipation problems or is otherwise undesirable, then the ICUTs on the wafer can be tested sequentially as a plurality of groups.
Because power and ground is supplied to the ICUTs via traces in scribe streets on the wafer, a probe card is not needed to supply power and ground to the ICUTs. Nor is a probe card needed to supply test information to an ICUT or to read test results back from an ICUT. An entire wafer of ICUTs can therefore be tested simultaneously without using a probe card to power any ICUT, and without using a probe ca
Kanzaki Kim
Nguyen Tung X.
Wallace T. Lester
Xilinx , Inc.
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