Redundancy for serial memory

Details Redundancy for serial memory Redundancy for serial memory

1990-01-12

1991-04-02

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Bad bit

365221, 36523002, 36523003, 36523005, 365240, 371 102, G11C 804, G06F 1120

Patent

active

050051580

ABSTRACT:
A fault tolerant sequential memory includes primary and redundant memory rows (or columns) and primary and redundant shift registers. The redundant memory rows (or columns) and redundant shift registers are formed at the end of the serial chain. Each shift register of each primary and redundant memory block is interconnected with an independent, separately programmable multiplexer logic circuit. Each multiplexer logic circuit includes an independently programmable repair buffer for logically bypassing a defective primary memory block and associated shift registers within the primary memory array. Each redundant memory block includes a multiplexer logic circuit having an independently programmable repair buffer for logically enabling a redundant memory block and shift register at the end of the serial chain. Consequently, a faulty memory block, including its shift register and memory row (or column) is bypassed and is effectively removed from the shifting sequence. The redundant memory block, including a redundant shift register and a redundant row (or column), is inserted at the end of the shift register chain by opening a programmable fuse element.

REFERENCES:
patent: 4254477 (1981-03-01), Hsia et al.
patent: 4386421 (1983-05-01), Inagaki
patent: 4630241 (1986-12-01), Kobayashi et al.

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