Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-01-30
2004-06-29
Guerrero, Maria (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S629000, C438S637000, C438S668000, C438S672000, C438S675000, C257S774000
Reexamination Certificate
active
06756304
ABSTRACT:
TITLE OF THE INVENTION
The invention relates to a method of fabricating conducting through-connections between the front face and the rear face of a substrate, as well as a substrate equipped with such conducting connections.
BACKGROUND OF THE INVENTION
The invention applies especially to substrates intended to accommodate a microelectronics structure, such as a sensor, a magnetic head or a microactuator, or intended to accommodate a microelectronics circuit.
The substrate may be electrically conducting (for example made of silicon, or of polysilicon) or insulating (for example made of ceramic).
The conducting through-connections make it possible to provide discrete electrical contacts between the front face and the rear face of a semiconducting, insulating or conducting substrate.
The use of conducting through-connections makes it possible:
to have a denser number of electrical contacts,
to provide electrical contacts over a stack of substrates,
to supply the components electrically from the rear face of the substrate when the wiring cannot be done on the front face.
The technique widely used to fabricate these conducting connections consists in piercing the substrate from front to back (for example by laser firing), in electrically insulating the hole (in the case of a semiconducting or conducting substrate) and in filling in the hole with a conducting material.
In the majority of applications, the filling of the holes has to be complete in order to allow the electrical contact to be picked up easily, in order to continue the technological stages relating to the front and rear faces after the fabrication of the conducting connections and in order to allow the electrical contact to be taken up after any thinning of the substrate at the end of the process.
The filling is generally done with a conducting paste injected under pressure (method used to form microelectronics packages). Although effective, this technique is fairly “violent” and gives rise to defects on the faces of the substrate (splinters, roughness, cracks, stresses, etc). This technique can even entail a loss of insulation in the case of semiconducting substrates. Furthermore, the paste is made up of metallic particles mixed with a solution based on polymers and solvents. This solution, which serves as a binder, has to be removed after filling. This removal causes a not inconsiderable shrinkage of the conducting material which can be the origin of holes which are responsible for loss of conduction. The paste may also be the origin of contamination, the polymers being difficult to remove.
Other techniques have been envisaged, in particular those described in the document “Electrical Interconnections Through Semiconductor Wafers” by T. R. Anthony, published in the magazine Journal Application of Physic 52(8) of August 1981. It covers:
the use of electrolysis methods, which generally lead to a surface filling of the hole due to problems of wetting and of edge effects or
the filling by a molten metal. This technique poses problems of thermal expansion. Metals with a low melting point (below the softening temperature of the substrate) exhibit a high coefficient of thermal expansion, often much higher than the substrate. This results in difficulties of a mechanical nature (stresses) or technological nature (risk of cracking of the deposited layers).
One of the objects of the invention is to alleviate the abovementioned drawbacks.
To that end, the subject of the invention is a method of fabricating conducting through-connections between the front face and the rear face of a substrate. The method consists:
in hollowing into the substrate, from the rear-face side, cavities having a depth and a cross section which are defined so as to delimit studs of defined cross section which are intended to provide for electrical conduction between the two faces and
in filling in the cavities with a dielectric material.
A further subject of the invention is a substrate equipped with conducting through-connections between its front face and its rear face. The conducting connections consist of studs delimited by the hollowing of cavities, in the rear face of the substrate. These cavities are filled in with a dielectric material.
The method consists in forming the conducting through-connections by delimiting in the substrate (semiconducting, insulating or conducting substrate) studs which will serve as conducting passages between the rear face and the front face of the substrate. The delimiting is performed by hollowing out cavities. The cavities are filled in with a dielectric material in order to provide for the mechanical strength and the electrical insulation of the studs.
The use of an insulant as a material for filling the hollowed cavities presents the advantage of offering a coefficient of thermal expansion close to that of the substrates widely used in microelectronics.
Furthermore, after filling, a thinning of the substrate on the two faces makes it possible to remove the short circuits due to the substrate and the surpluses of filling material.
The invention moreover has the advantage that it allows:
easy picking-up of the electrical contact, even after thinning of the substrate, and
very good electrical insulation of the conducting passages.
The substrate may be insulating (for example of ceramic) or slightly conducting (for example of lightly doped semiconductor). In these cases a metallic deposit is formed or can be formed on the studs before filling of the cavities in order to provide the electrical conductivity of the studs.
In the case of the use of a silicon substrate of silicon-on-insulator type, better known by the acronym SOI, the thinning of the substrate which is intended to cut the short circuits after filling can be replaced by etching of the silicon and oxide layers on the front-face side in order to make the studs show through.
A substrate equipped with conducting through-connections which are obtained by a method according to the invention can play a part in delimiting an enclosure. The substrate may make it possible to seal the enclosure in such a way that the atmosphere in the enclosure is perfectly defined with, in particular, a pressure capable of being used as a reference pressure. The leaktightness of the substrate is not in any way affected by the conducting through-connections consisting of the studs. This is because, on the one hand, the conducting through-connections obtained by a method according to the invention leave the front face of the substrate perfectly flat and, on the other hand, the dielectric material fills in the cavity in a completely hermetic way. The possibility of being able to carry out sealing plays a vital role, in particular for the fabrication of microsensors.
REFERENCES:
patent: 4566186 (1986-01-01), Bauer et al.
patent: 4978639 (1990-12-01), Hua et al.
patent: 5056216 (1991-10-01), Madou et al.
patent: 5343071 (1994-08-01), Kazior et al.
patent: 5674785 (1997-10-01), Akram et al.
patent: 6013948 (2000-01-01), Akram et al.
patent: 6271135 (2001-08-01), Palmans et al.
patent: 6392158 (2002-05-01), Caplet et al.
patent: 6475889 (2002-11-01), Ring
patent: 0 926 726 (1999-06-01), None
patent: 63-193545 (1988-08-01), None
Arai (JP63-193545), Aug. 1988, English Abstract.*
A. Guldan et al.: “Method for producing via-connections in semiconductor wafers using a combination of plasma and chemical etching” IEEE Transactions on Electron Devices, US, IEEE Inc., vol. ED-30, No. 10, pp. 1402-1403.
Guerrero Maria
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Thales Avionics S.A.
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