Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-09-19
2004-10-19
Chen, Jack (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S645000, C438S687000
Reexamination Certificate
active
06806185
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming damascene structures within microelectronic fabrications. More particularly, the present invention relates to methods for forming low dielectric constant damascene structures within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly common in the art of microelectronic fabrication to employ interposed between the patterns of patterned microelectronic conductor layers when fabricating microelectronic fabrications microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, such comparatively low dielectric constant dielectric materials generally having dielectric constants in a range of from about 2.0 to less than about 3.0. For comparison purposes, microelectronic dielectric layers formed within microelectronic fabrications from conventional silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials typically have comparatively high dielectric constants in a range of from greater than about 4.0 to about 8.0. Similarly, such patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials are typically formed within microelectronic fabrications while employing damascene methods, including in particular dual damascene methods.
Microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials are desirable in the art of microelectronic fabrication formed interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications insofar as such microelectronic dielectric layers formed of dielectric materials having comparatively low dielectric constants provide microelectronic fabrications which may theoretically operate at higher microelectronic fabrication speeds, with attenuated patterned microelectronic conductor layer parasitic capacitance and attenuated patterned microelectronic conductor layer cross-talk.
Similarly, damascene methods are desirable in the art of microelectronic fabrication for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials insofar as damascene methods are comparatively simple fabrication methods which may often be employed to fabricate microelectronic structures which are not otherwise practicably accessible in the art of microelectronic fabrication.
While damascene methods are thus desirable in the art of microelectronic fabrication for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials within microelectronic fabrications, damascene methods are nonetheless not entirely without problems in the art of microelectronic fabrication for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials within microelectronic fabrications. In that regard, while damascene methods are generally successful for forming patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials within microelectronic fabrications, such damascene methods often provide abrasive damage, such as but not limited to voids, to the microelectronic dielectric layers formed of the comparatively low dielectric constant dielectric materials.
It is thus desirable in the art of microelectronic fabrication to provide damascene methods which may be employed in the art of microelectronic fabrication for providing patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, with attenuated abrasive damage to the microelectronic dielectric layers formed of the comparatively low dielectric constant dielectric materials.
It is towards the foregoing object that the present invention is directed.
Various methods and apparatus have been disclosed in the art of microelectronic fabrication for forming microelectronic layers, and in particular microelectronic dielectric layers, with desirable properties in the art of microelectronic fabrication.
Included among the methods and apparatus, but not limited among the methods and apparatus, are methods and apparatus disclosed within: (1) Yau et al., in U.S. Pat. No. 6,072,227 (a method and an apparatus for forming within a microelectronic fabrication, and with enhanced barrier properties and enhanced etch stop properties, a microelectronic dielectric layer formed of a lower dielectric constant dielectric material formed employing a plasma enhanced chemical vapor deposition (PECVD) method employing a silicon source material comprising an organosilane, preferably methylsilane, along with an oxidant source material, preferably nitrous oxide; (2) Mandal et al., in U.S. Pat. No. 6,107,184 and U.S. Pat. No. 6,171,945 (methods and apparatus for forming within a microelectronic fabrication a microelectronic dielectric layer formed of a comparatively low dielectric constant dielectric material comprising a nanoporous organic copolymer dielectric material or a nanoporous silicon oxide based dielectric material; and (3) Sukharev et al., in U.S. Pat. No. 6,114,259 (a method for treating within a microelectronic fabrication exposed portions of a microelectronic dielectric layer formed of a comparatively low dielectric constant carbon doped silicon oxide dielectric material such as to avoid subsequent oxidizing plasma etch damage to the microelectronic dielectric layer).
Desirable in the art of microelectronic fabrication are damascene methods and materials which may be employed in the art of microelectronic fabrication for providing patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, with attenuated abrasive damage to the microelectronic dielectric layers.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a damascene method for forming within a microelectronic fabrication a patterned microelectronic conductor layer having formed interposed between its patterns a microelectronic dielectric layer formed of a comparatively low dielectric constant dielectric material.
A second object of the present invention is to provide a damascene method in accord with the first object of the present invention, wherein the patterned microelectronic conductor layer is formed with attenuated abrasive damage to the microelectronic dielectric layer.
A third object of the present invention is to provide a damascene method in accord with the first object of the present invention and the second object of the present invention, wherein the damascene method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a damascene method for forming a patterned microelectronic conductor layer within a microelectronic fabrication.
To practice the method of the present invention, there is first
Ko Chung-Chi
Li Lain-Jong
Chen Jack
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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