Thin-film transistor and method of making same

Details Thin-film transistor and method of making same Thin-film transistor and method of making same

2003-03-04

2004-11-09

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S155000, C438S481000, C438S482000, C438S483000, C438S588000

Reexamination Certificate

active

06815321

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin-film transistor of a liquid crystal display and, more particularly, to a thin-film transistor having a gate including a double-layered metal structure and a method of making such a double-layered metal gate.
2. Discussion of Related Art
An LCD (Liquid Crystal Display) includes a switching device as a driving element, and a pixel-arranged matrix structure having transparent or light-reflecting pixel electrodes as its basic units. The switching device is a thin-film transistor having gate, source and drain regions.
The gate of the thin-film transistor is made of aluminum to reduce its wiring resistance, but an aluminum gate may cause defects such as hillock.
A double-layered metal gate, i.e., molybdenum-coated aluminum gate is considered as a substitute for the aluminum gate to overcome the problem of the hillock.
To fabricate a double-layered gate, metals such as aluminum and molybdenum are sequentially deposited, followed by a patterning process carried out via photolithography to form resulting metal films which have the same width. Although the double-layered gate is desirable to overcome the problem of hillock, the resulting deposited metal films forming the double-layered gate are so thick that a severe single step is created by a thickness difference between the metal films and a substrate, thereby causing a single step difference between the substrate and the double-layered gate which deteriorates the step coverage of a later formed gate oxide layer. The source and drain regions formed on the gate oxide layer may have disconnections between areas of the source and drain regions which are overlapped and non-overlapped with the gate, or electrically exhibit short circuits as a result of contact with the gate.
According to another method of forming the gate, each of the metal layers of Al and Mo form a double step difference with the substrate so as to improve the step coverage of the gate oxide layer.
FIGS. 1A through 1F
are diagrams illustrating the process for fabricating a thin-film transistor of a method which is related to the invention described and claimed in the present application. The method shown in
FIGS. 1A-1F
is not believed to be published prior art but is merely a recently discovered method related to the invention described and claimed in the present application.
Referring to
FIG. 1A
, aluminum is deposited on a substrate
11
to form a first metal layer
13
. A first photoresist
15
is deposited on the first metal layer
13
. The first photoresist
15
is exposed and developed so as to have a certain width w1 extending along the first metal layer
13
.
Referring to
FIG. 1B
, the first metal layer
13
is patterned via wet etching using the first photoresist
15
as a mask so that the first metal layer
13
has a certain width w1. After the first photoresist
15
is removed, a second metal layer
17
is formed by depositing Mo, Ta, or Co on the substrate
11
so as to cover the first metal layer
13
. A second photoresist
19
is then deposited on the second metal layer
17
. The second photoresist
19
is exposed and developed so as to have a certain width w2 extending along the second metal layer
17
and located above the first metal layer
13
.
Referring to
FIG. 1C
, the second metal layer
17
is patterned via a wet etching process using the second photoresist
19
as a mask such that the second metal layer
17
has a certain width w2 which is narrower than the width w1 of the first metal layer
13
. After formation of the gate
21
, the second photoresist
19
is removed.
Thus, the patterned first and second metal layers
13
and
17
form a gate
21
having a double-layered metal structure that provides double step difference between the double-layered metal gate structure
21
and the substrate
11
. The formation of the gate
21
as described above and shown in
FIGS. 1A-1F
requires the use of two photoresists
15
,
19
and two photoresist steps.
In the gate
21
, shown in
FIG. 1C
, the second metal layer
17
is preferably centrally located on the first metal layer
13
. Although there is no specific information available regarding a relationship of w1 to w2 of this related art method, based on their understanding of this related method resulting in the structure shown in
FIG. 1C
, the inventors of the invention described and claimed in the present application assume that the width difference w1−w2 between the first and second metal layers
13
and
17
is larger than or equal to 4 &mgr;m, that is, w1−w2≧4 &mgr;m.
Referring to
FIG. 1D
, a first insulating layer
23
is formed by depositing silicon oxide SiO
2
or silicon nitride Si
3
N
4
as a single-layered or double-layered structure on the gate
21
and substrate
11
. Semiconductor and ohmic contact layers
25
and
27
are formed by sequentially depositing undoped polycrystalline silicon and heavily doped silicon on the first insulating layer
23
. The semiconductor and ohmic contact layers
25
and
27
are patterned to expose the first insulating layer
23
by photolithography.
Referring to
FIG. 1E
, conductive metal such as aluminum is laminated on the insulating and ohmic contact layers
23
and
27
. The conductive metal is patterned by photolithography so as to form source electrode
29
and a drain electrode
31
. A portion of the ohmic contact layer
27
exposed between the source and drain electrodes
29
and
31
is etched by using the source and drain electrodes
29
and
31
as masks.
Referring to
FIG. 1F
, silicon oxide or silicon nitride is deposited on the entire surface of the structure to form a second insulating layer
33
. The second insulating layer
33
is etched to expose a designated portion of the drain electrode
31
, thus forming a contact hole
35
. By depositing transparent and conductive material on the second insulating layer
33
and patterning it via photolithography, a pixel electrode
37
is formed so as to be electrically connected to the drain electrode
31
through the contact hole
35
.
According to the method of fabricating a thin-film transistor as described above and shown in
FIGS. 1A-1F
, respective first and second metal layers are formed through photolithography using different masks so as to form the gate with a double-layered metal structure, resulting in double step differences between the gate and substrate.
As a result of the double step difference between the gate
21
and the substrate
11
shown in
FIG. 1C
, a hillock often occurs on both side portions of the first metal layer
13
which have no portion of the second metal layer
17
deposited thereon when the first metal layer
13
is wider than the second metal layer
17
as in FIG.
1
C. Another problem with this related art method is that the process for forming a gate is complex and requires two photoresists
15
,
19
and two steps of deposition and photolithography. As a result, the contact resistance between the first and second metal layers may be increased.
Another related art method of forming a double metal layer gate structure is described in “Low Cost, High Quality TFT-LCD Process”, SOCIETY FOR INFORMATION DISPLAY EURO DISPLAY 96, Proceedings of the 16
th
International Display Research Conference, Birmingham, England, Oct. 1, 1996, pages 591-594. One page 592 of this publication, a method of forming a double metal gate structure includes the process of depositing two metal layers first and then patterning the two metal layer to thereby eliminate an additional photoresist step. However, with this method, process difficulties during the one step photoresist process for forming the double metal layer gate resulted in the top layer being wider than the bottom layer causing an overhang condition in which the top layer overhangs the bottom layer. This difficulty may result in poor step coverage and disconnection. This problem was solved by using a three-step etching process in which the photoresist had to be baked before each of the three etching steps to avo

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