Ferroelectric memory device comprising redundancy circuit

Details Ferroelectric memory device comprising redundancy circuit Ferroelectric memory device comprising redundancy circuit

2003-06-30

2004-12-28

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S145000

Reexamination Certificate

active

06836439

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to ferroelectric memory devices, and more specifically, to a new structure and a redundancy circuit designed to be suitable for the new cell structure.
2. Description of the Related Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a DRAM (Dynamic Random Access Memory) and conserves data even after the power is turned off.
The FRAM includes capacitors similar to the DRAM, but the capacitors have a ferroelectric substance for utilizing the characteristic of a high residual polarization of the ferroelectric substance in which data is not low even after eliminating an electric field applied thereto.
FIG. 1
is a characteristic curve illustrating a hysteresis loop of a general ferroelectric substance. As shown in
FIG. 1
, a polarization induced by an electric field does not vanish but keeps some strength (‘d’ or ‘a’ state) even after the electric field is cleared due to existence of a residual (or spontaneous) polarization. These ‘d’ and ‘a’ states may be assigned to binary values of ‘1’ and ‘0’ for use as a memory cell.
FIG. 2
is a structural diagram illustrating a unit cell of the FRAM device. As shown in
FIG. 2
, the unit cell of the conventional FRAM is provided with a bitline BL arranged in one direction and a wordline WL arranged in another direction vertical to the bitline BL. A plateline PL is arranged parallel to the wordline and spaced at a predetermined interval. The unit cell is also provided with a transistor T
1
having a gate connected to an adjacent wordline WL and a source connected to an adjacent bitline BL, and a ferroelectric capacitor FC
1
having the first terminal of the two terminals connected to the drain terminal of the transistor T
1
and the second terminal of the two terminals connected to the plateline PL.
FIG. 3
a
is a timing diagram illustrating a write mode of the conventional FRAM while
FIG. 3
b
is a timing diagram illustrating a read mode of the conventional FRAM.
Referring to
FIG. 3
a,
when a chip enable signal CSBpad applied externally transits from a high to low level and simultaneously a write enable signal WEBpad also transits from a high to low level, the array is enabled to start a write mode. Thereafter, when an address is decoded in a write mode, a pulse applied to a corresponding wordline transits from a “low” to “high” level, thereby selecting the cell.
In order to write a binary logic value “1” in the selected cell, a “high” signal is applied to a bitline BL while a “low” signal is applied to a plateline PL. In order to write a binary logic value “0” in the cell, a “low” signal is applied to a bitline BL while a “high” signal is applied to a plateline PL.
Referring to
FIG. 3
b,
when a chip enable signal CSBpad externally transits from a “high” to “low” level, all bitlines are equalized to a “low” level by an equalization signal before selection of a required wordline.
After each bitline is deactivated, an address is decoded to transit a signal on the required wordline from a “low” to “high” level, thereby selecting a corresponding unit cell. A “high” signal is applied to a plateline of the selected cell to cancel a data Qs corresponding to the logic value “1” stored in the FRAM. If the logic value “0” is stored in the FRAM, a corresponding data Qns will not be destroyed.
The destroyed and non-destroyed data output different values, respectively, according to the above-described hysteresis loop characteristics. As a result, a sense amplifier senses logic values “1” or “0”. In other words, as shown in the hysteresis loop of
FIG. 1
, the state moves from ‘d’ to ‘f’ when the data is destroyed while the state moves from ‘a’ to ‘f’ when the data is not destroyed.
As a result, the destroyed data amplified by the enabled sense amplifier outputs a logic value “1” while the non-destroyed data amplified by the sense amplifier outputs a logic value “0”. The original data is destroyed after the sense amplifier amplifies the data. Accordingly, when a “high” signal is applied to the required wordline, the plateline is disabled from “high” to “low”, thereby recovering the original data.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a ferroelectirc memory device having a bitline structure comprising a main bitline MBL and a sub bitline SBL, wherein the main bitline MBL is connected to a plurality of sub bitlines via switches. Therefore, the driving load of the bitline is reduced to that of one sub bitline SBL, and a driving speed is improved.
It is another object of the present invention to provide a redundancy circuit for the ferroelectric memory device having the above-described structure.
The disclosed ferroelectric memory device comprises a main cell array, a row redundancy cell array, a first column redundancy cell array, a second column redundancy cell array, a main bitline pull-up controller, and a column selection controller.
The main cell array includes a bitline structure comprising a main bitline and a sub bitline. The row redundancy cell array is configured to share the main bitlines with the main cell array. The first column redundancy cell array is configured to share wordlines and platelines with the main cell array. The second column redundancy cell array is. configured to share redundancy wordlines and redundancy platelines with the row redundancy cell array, and to share redundancy main bitlines with the first column redundancy. The main bitline pull-up controller pulls up main bitlines and the redundancy main bitlines in response to first control signals, respectively. The column selection controller connects data bus lines to the main bitlines and the redundancy main bitlines in response to column selection signals, respectively.


REFERENCES:
patent: 6058053 (2000-05-01), Tsuji et al.
patent: 6084807 (2000-07-01), Choi
patent: 6201744 (2001-03-01), Takahashi
patent: 6240007 (2001-05-01), Kang
patent: 6317355 (2001-11-01), Kang
patent: 6377498 (2002-04-01), Kang
patent: 6510071 (2003-01-01), Oowaki

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