Electrical computers and digital data processing systems: input/ – Access arbitrating
Reexamination Certificate
2001-06-07
2004-11-30
Dang, Khanh (Department: 2111)
Electrical computers and digital data processing systems: input/
Access arbitrating
C710S242000, C326S094000, C327S198000
Reexamination Certificate
active
06826642
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for implementing a discriminator circuit generally and, more particularly, to a metastable insensitive circuit configured to arbitrate between requests based on pulse discriminators.
BACKGROUND OF THE INVENTION
Hardware devices are employed within computer systems to assist in determining the availability of computer resources (i.e., a memory chip, a hard disk drive, etc.) which can only be controlled and accessed by one requesting device at a time. However, metastable conditions can exist when contention between requests from different devices occurs. Arbitrators (or arbiters) have been designed to reduce bus contention through flags (or other such means). However, arbitrators can enter metastable states during simultaneous requests. Conventional arbitrators can therefore enter an undecided state and remain for an indefinite period of time, causing undesirable results (i.e., a system crash or hang, etc.).
Referring to
FIG. 1
, a circuit
10
is shown illustrating a conventional arbitration circuit. The circuit
10
comprises a NAND gate
12
, a NAND gate
14
and an interlock circuit
16
. The NAND gate
12
receives the signal A and an output from the NAND gate
14
. The NAND gate
14
receives a signal B and an output from the NAND gate
12
. The interlock circuit
16
presents a signal OUTA and a signal OUTB in response to the signal from the NAND gates
12
and
14
. The NAND gates
12
and
14
are implemented in a cross-coupled configuration. Therefore, the NAND gates
12
and
14
can enter a metastable condition.
Referring to
FIG. 2
, a timing diagram of the circuit
10
is shown. The input A and the input B are shown crossing between a time T
1
and a time T
2
. The period between the time T
1
and T
2
illustrates the metastable event which can cause a push out. The circuit
10
is subject to metastability when the inputs A and B change states simultaneously.
The interlock circuit
16
attempts to resolve metastable states, but does not prevent metastable events. The arbitration circuit
10
implements cross coupled NAND arbiters (
12
and
14
) which cause delays due to metastable events. The resolution (or recovery) time of the cross coupled arbiters
12
and
14
is not predictable. While the interlock circuit
16
can try to prevent metastable states from occurring on the outputs, the interlock circuit
16
does not resolve the occurrence of the metastable events. Conventional arbitrators attempt to reduce the probability of metastable occurrences rather than eliminate such occurrences.
It is desirable to provide a method and/or architecture that eliminates metastable conditions due to simultaneous requests.
SUMMARY OF THE INVENTION
One aspect of the present invention concerns an apparatus comprising a margin logic circuit, one or more discriminator circuits and a sense circuit. The margin logic circuit may be configured to receive a plurality of requests and present one or more control signals. The one or more discriminators may be configured to (i) present one or more leading access signals and (ii) receive the one or more control signals and the plurality of requests. The sense circuit may be configured to receive the one or more leading access signals and the plurality of requests and present grant access signal. The sense circuit may be configured to reduce the effects of metastable conditions.
Another aspect of the present invention concerns an apparatus comprising a first one or more threshold devices, a second one or more threshold devices and a logic device. The first one or more threshold devices may be configured to control an output. The second one or more threshold devices may be configured to receive the output. The logic device may be (i) coupled to the second one or more threshold devices and (ii) configured to provide a feedback to the first one or more threshold devices. The feedback may be configured to force a reset condition if a metastable event occurs.
The objects, features and advantages of the present invention include providing an arbitration circuit based on pulse discriminators that may (i) reduce the effects of metastable conditions, (ii) effect arbitration between two (or more) asynchronous requests, (iii) reduce delays associated with metastable events, and/or (iv) force a reset of a metastable condition.
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Cypress Semiconductor Corp.
Dang Khanh
Maiorana P.C. Christopher P.
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