Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-05-15
2004-11-09
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C473S606000, C473S505000, C473S505000, C473S505000
Reexamination Certificate
active
06815340
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present invention relates to forming an electroless nucleation layer on a via bottom.
BACKGROUND OF THE INVENTION
Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of IC devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC. Nevertheless, there are many factors that make the continued miniaturization of ICs difficult. For example, as the size of vias (or pathways between integrated circuit layers used to electrically connect separate conductive layers) decreases, electrical resistance increases.
Conventional integrated circuits utilize vias to connect structures (e.g., gates, drain regions, source regions) and conductive lines. For example, a via can connect a gate above the substrate to a conductor line in a metal
1
layer. Vias can also interconnect conductive lines. For example, a via can connect a conductive line in a metal
1
layer to a conductor line in a metal
2
layer. A via is typically a metal plug which extends through an insulative layer in a multilayer integrated circuit. Vias and barrier layers are discussed in U.S. Pat. Nos. 5,646,448; 5,770,519; and 5,639,691; each of which are assigned to the assignee of the present application. A barrier layer is used to protect the via and insulative layer from metal diffusion and the via and conductive line from electromigration (EM). The barrier layer can contribute significantly to resistance associated with the via metal. Electromigration is the mass transport due to momentum exchange between conducting electrons and diffusing metal atoms. Electromigration causes progressive damage to the metal conductors in an integrated circuit. In general, metals are most susceptible to electromigration at very high current density and temperatures of 100° C. or more.
Integrated circuit manufacturers have attempted to reduce via resistance as the via size decreases by reducing the thickness of the barrier material. According to a conventional plasma vapor deposition (PVD) process, IC manufacturers deposit a very thin barrier material at the bottom of the via due to non-conformal deposition. The thickness of the barrier material is reduced by chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes. These advanced deposition processes form highly conformal barrier metal films. However, reducing the barrier thickness causes the barrier to become more permeable to copper (Cu) diffusion, which can adversely affect resistance to electromigration.
A conventional integrated circuit can include a copper layer, a copper via, a copper layer, a dielectric layer, and a dielectric layer. The via and copper layer are separated by a barrier layer.
The integrated circuit can also include a dielectric layer that is separated from the copper layer by an etch stop layer. The dielectric layer can be oxide and the etch stop layer can be Silicon Nitride (SiN). The etch stop layer prevents diffusion of copper from the copper layer into the dielectric layer. The dielectric layer can be separated from the copper layer by a barrier layer. Barrier layers can be Tantalum Nitride (TaN). Etch stop layers can be Silicon Nitride (SiN).
According to conventional processes, the barrier layer can have a cross-sectional thickness of between 7 nm to 25 nm. The barrier layer inhibits diffusion of copper ions from layers into the via and from the via into the dielectric layer. Conventional barrier layers can include Tantalum Nitride (TaN).
As discussed above, conventional systems have attempted to reduce the thickness of the barrier layer to reduce the resistance associated with the via. However, this reduction in thickness can cause electromigration failures.
Electromigration failures have been described by Stanley Wolf, Ph.D. in
Silicon Processing for the VLSI Era
, Lattice Press, Sunset Beach, Calif., Vol. 2, pp. 264-65 (1990). Dr. Wolf explains that a positive divergence of the motion of the ions of a conductor leads to an accumulation of vacancies, forming a void in the metal. Such voids may ultimately grow to a size that results in open-circuit failure of the conductor line.
Thus, there is a need for a barrier that is more resistant to copper diffusion. Further, there is a need for a method of forming an electroless nucleation layer on a via bottom. Even further, there is a need for a method of enhancing barrier properties by providing an electroless nucleation layer on a via bottom.
SUMMARY OF THE INVENTION
An exemplary embodiment is related to a method of fabricating an integrated circuit. This method can include performing a reactive ion etch (RIE) to form a via aperture in a dielectric layer where the via aperture exposes a portion of a conductive layer located under the dielectric layer, removing polymer residue from the RIE, and forming a nucleation layer over the exposed portion of the conductive layer using an alloy.
Another exemplary embodiment is related to a method of forming a nucleation layer at a location intermediate a conductive layer and a via. This method can include providing a conductive layer over an integrated circuit substrate, performing a reactive ion etching (RIE) etch to form a via aperture in a dielectric layer positioned over the conductive layer, removing residue from the RIE etch, and providing a nucleation layer at the bottom of the via aperture, proximate the conductive layer.
Another exemplary embodiment is related to a method of forming a via in an integrated circuit. This method can include depositing a first conductive layer, depositing an etch stop layer over the first conductive layer, depositing an insulating layer over the etch stop layer, forming an aperture in the insulating layer and the etch stop layer, depositing an alloy element to form a nucleation layer at a bottom of the aperture above the first conductive layer, filling the aperture with a via material including a second alloy element to form a via, and providing a second conductive layer over the via such that the via electrically connects the second conductive layer t o the first conductive layer.
Other principle features and advantages of the invention will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims.
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Wolf et al., Silicon Processing in the VLSI Era, vol. 2, (Lattice Press, California) 1990, p. 264-65.
Besser Paul R.
Buynoski Matthew S.
Lopatin Sergey D.
Wang Pin-Chin Connie
Advanced Micro Devices , Inc.
Foley & Lardner LLP
Lebentritt Michael S.
Wilson Christian
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