Bit line load circuit

Details Bit line load circuit Bit line load circuit

1993-12-27

1996-04-16

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Including signal clamping

36518911, 365190, G11C 700

Patent

active

055089615

ABSTRACT:
A bit line load circuit for a static random access memory comprising first and second P-channel MOSFETs for clamping a voltage difference between first and second bit lines at a predetermined level in a data reading operation and third and fourth P-channel MOSFETs for blocking a DC current flow to one of the first and second bit lines having a "low" level and performing a voltage compensation for the other having a "high" level in a data writing operation. The first bit line is active "high" and the second bit line is active "low". The first P-channel MOSFET has a drain connected to the first bit line, a source connected to a power source line and a gate connected to a write enable signal, the second P-channel MOSFET has a drain connected to the second bit line, a source connected to the power source line and a gate connected to the write enable signal, the third P-channel MOSFET has a drain connected to the first bit line, a source connected to the power source line and a gate cross-connected to the second bit line arid the fourth P-channel MOSFET has a drain connected to the second bit line, a source connected to the power source line and a gate cross-connected to the first bit line.

REFERENCES:
patent: 4386419 (1983-05-01), Yamamoto
patent: 4802128 (1989-01-01), Watanabe et al.
patent: 4985864 (1991-01-01), Price
patent: 5126974 (1992-06-01), Sasaki et al.
patent: 5305264 (1994-04-01), Takahashi

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