Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-06-26
2004-08-24
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06782517
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of photolithography, and more particularly to photomask and integrated circuit manufactured by automatically eliminating design rule violations during construction of a mask layout block.
BACKGROUND OF THE INVENTION
Over the past several years, the number of transistors in a semiconductor device has increased dramatically. Due to this increase, the time to design and manufacture semiconductor devices has also increased.
A typical semiconductor design process includes numerous steps. Initially, a circuit designer prepares a schematic diagram that includes logical connections between logic elements that together form an integrated circuit. The schematic diagram is then tested to verify that the logic elements and associated logical connections perform a desired function. Once the circuit is verified, the schematic diagram is converted into a mask layout database that includes a series of polygons. The polygons may represent the logic elements and the logical connections contained in the schematic diagram. The mask layout database is then converted into multiple photomasks, also know as masks or reticles, that may be used to image different layers of the integrated circuit on to a semiconductor wafer.
Typically, the mask layout database is created manually by a layout designer or automatically by a synthesis tool. In a 0.13 micron or below manufacturing process, the layout designer or synthesis tool may have to use thousands of design rules to create the mask layout database. The large number of design rules adds complexity to the layout design process because the layout designer may have to memorize or constantly look up the design rules to place polygons in the mask layout database. Since the process may be completely manual, the layout designer may create design rule violations during the construction of the mask layout database. In order to correct the design rule violations, spacing between polygons on the same layer and dimensions of polygons are compared to the design rules included in a technology file for a desired manufacturing process. This comparison may identify design rule violations if the spacing between the polygons or the dimensions of the polygons in the mask layout database is less than the corresponding minimum allowable design rule in the technology file.
Today, any design rule violations in the mask layout database are corrected manually by a layout designer. The layout designer typically finds each violation and manually corrects the violations by moving polygons associated with the violations. During the correction process, the layout designer may create new design rule violations and, therefore, the correction process may be repeated until the mask layout database does not include any design rule violations. The process of iteratively correcting the design rule violations may take several hours or even days to complete and can increase the time needed to design the integrated circuit. The additional time required to complete layout may also delay the production of a photomask set used to fabricate the integrated circuit.
SUMMARY OF THE INVENTION
In accordance with the present invention, the disadvantages and problems associated with eliminating design rule violations on a photomask have been substantially reduced or eliminated. In a particular embodiment, a photomask is formed by using a mask pattern file created by automatically preventing a polygon from being placed in a selected position in a mask layout block if a design rule violation is identified.
In accordance with one embodiment of the present invention, a photomask includes a patterned layer formed on at least a portion of a substrate. The patterned layer may be formed using a mask pattern file that is created by analyzing a selected position of a polygon in a mask layout block and identifying a design rule violation in the mask layout block if the selected position is less than a design rule from a technology file. If the design rule violation is identified, the placement of the polygon at the selected position is automatically prevented.
In accordance with another embodiment of the present invention, an integrated circuit includes a plurality of interconnect layers, including but not limited to n-well, p-well, diffusion, polysilicon and metal, and a plurality of contact layers that provide electrical connections between the respective interconnect layers. The interconnect and contact layers may be formed using a plurality of photomasks that are created by analyzing a selected position of a polygon in a mask layout block and identifying a design rule violation in the mask layout block if the selected position is less than a design rule from a technology file. If the design rule violation is identified, the placement of the polygon at the selected position is automatically prevented.
Important technical advantages of certain embodiments of the present invention include a clean-by-construction (CBC) tool that prevents design rule violations from being created during the construction of a mask layout block. A layout designer may move a cursor on a display device over a polygon in order to select the polygon. The CBC tool highlights an area that may represent a space in the layout block where polygons may be placed without violating any of the design rule constraints contained in a technology file. If the layout designer attempts to move the polygon outside of the highlighted area, the CBC tool prevents the layout designer from placing the polygon in the desired position and automatically places the polygon in a position located inside the highlighted area. The mask layout block, therefore, may be created free of design rule violations.
Another important technical advantage of certain embodiments of the present invention includes a CBC tool that reduces the design time for an integrated circuit. In a typical integrated circuit design process, a design rule check (DRC) tool analyzes a mask layout file for design rule violations and identifies any violations in an output file. A layout designer may use the output file to manually eliminate the identified design rule violations. In contrast, the present invention may eliminate design rule violations from a mask layout block before the mask layout block is converted into a mask layout file. The time needed to complete the design process for the integrated circuit, therefore, may be substantially reduced since the steps of checking the layout with a DRC tool and correcting the identified design rule violations may be eliminated.
All, some, or none of these technical advantages may be present in various embodiments of the present invention. Other technical advantages will be readily apparent to one skilled in the art from the following figures, descriptions, and claims.
REFERENCES:
patent: 5168001 (1992-12-01), Legare et al.
patent: 5536955 (1996-07-01), Ali
patent: 5781446 (1998-07-01), Wu
patent: 6009251 (1999-12-01), Ho et al.
patent: 6122443 (2000-09-01), Nishikawa
Xue et al., “A Net-Oriented Method for Realistic Fault Analysis”, Nov. 1993, IEEE/ACM International Conference on Computer-Aided Design,Digest of Technical Papers pp. 78 -83.*
Allan et al., “Efficient Critical Area Algorithms and their Application to Yield Improvement and Test Strategies”, Oct. 1994, IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, Proceedings pp. 88 -96.*
Allan et al., “Critical Area Extraction for Soft Fault Estimation” Feb. 1998, IEEE Transactions on Semiconductor Manufacturing, vol. 11, iss. 1, pp. 146 -154.*
Segal et al., “Predicting Failing Bitmap Signatures for Memory Arrays with Critical Area Analysis”, Sep. 1999, IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, paper pp. 178 -182.*
U.S. Application Ser. No. 10/180,177 entitled “System and Method For Eliminating Design Rule Violations During Construction of a Mask Layout Block,” filed by Dan Rittman et al. on Jun. 26, 2002.
Oren Micha
Rittman Dan
Baker & Botts L.L.P.
DuPont Photomasks, Inc.
Lin Sun James
Siek Vuthe
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