Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-11-13
2004-08-17
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000
Reexamination Certificate
active
06777320
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to microelectronic structures and fabrication methods, and more particularly to in-plane decoupling capacitor structures and methods of making the same.
2. Background
Advances in semiconductor manufacturing technology have led to the development of integrated circuits having multiple levels, of interconnect. In such an integrated circuit, patterned conductive material on one interconnect level is electrically insulated from patterned conductive material on another interconnect level by films of material such as silicon dioxide. These patterned conductive materials are also referred to as interconnect lines. The spaced apart interconnect lines on each interconnect level are typically provided with insulating material therebetween The interconnect lines on each interconnect level are typically substantially co-planar. Connections between the conductive material at the various interconnect levels are made by forming openings in the insulating layers and providing an electrically conductive structure such that the patterned conductive material from different interconnect levels are brought into electrical contact with each other. These structures are often referred to as contacts or vias.
A consequence of having many interconnect lines separated by an insulating layer is the formation of undesired capacitors. The parasitic capacitance between patterned conductive material, or more simply, interconnects, separated by insulating material on microelectronic devices contributes to effects such as RC delay, power dissipation, and capacitively coupled signals, also known as cross-talk. In view of the adverse effects of parasitic capacitance on the performance of integrated circuits, it is desirable to reduce the capacitance between interconnect lines. One way to reduce the unwanted capacitance between the interconnects is to use an insulating material with a lower dielectric constant.
Unlike parasitic capacitance between interconnect lines, which adversely affects circuit performance, decoupling capacitance is used to make circuits more robust in the presence of power supply noise. Decoupling capacitors are typically formed between power supply nodes. In this way, the rail-to-rail voltage across a circuit is protected to some degree from noise-induced voltage excursions in the power rails. Decoupling capacitors are often formed external to an integrated circuit, or may even be incorporated into the packaging of an integrated circuit.
What is needed is a structure that provides on-chip relatively high valued decoupling capacitors between power supply nodes, while providing low capacitance between interconnect lines that are used to carry signals. What is further needed are methods of making such a structure.
SUMMARY OF THE INVENTION
Briefly, an interconnect structure for microelectronic devices includes a plurality of patterned, spaced apart, substantially co-planar, conductive lines, a first portion of the plurality of conductive lines having a first intralayer dielectric of a first dielectric constant therebetween, and second portion of the plurality of conductive lines having a second intralayer dielectric of a second dielectric constant therebetween.
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Chiang Chien
Fraser David B.
Blakley Sokoloff Taylor & Zafman LLP
Intel Corporation
Malsawma Lex H.
Smith Matthew
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