Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-03-26
2004-12-21
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S408000, C257S409000, C257S410000, C257S411000, C257S413000, C438S216000, C438S585000
Reexamination Certificate
active
06833596
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, the present invention relates to a gate electrode layer of transistors.
2. Description of the Related Art
Conventionally, polycrystalline silicon has been mainly used as the material of a gate electrode layer of MOS transistors (hereinafter, referred to as MOSFET). This is based on the following reasons. The above polycrystalline silicon stabilizes the interface state between a gate electrode layer and a gate insulating film (gate oxide film) existing under gate electrode layer, and is excellent in mutual adhesion. In addition, impurity elements introduced into the polycrystalline silicon are properly selected, and thereby, in N-type and P-type MOSFETs, it is possible to form a gate electrode layer having the optimal work function, and to control threshold voltage values.
However, with the development of micro-fabrication in MOSFET, depletion in the gate electrode layer must be considered as a serious problem incapable of disregarding. More specifically, the above depletion of the gate electrode layer is that when voltage is applied to the gate electrode layer, a depletion layer is formed at a gate electrode layer region near to the interface between the gate electrode layer and the gate insulating film.
The cause of the depletion of the gate electrode layer arises from the reason why a polycrystalline silicon film is used as the material of semiconductors. In N-type and P-type MOSFETs, the polycrystalline silicon film functions as the gate electrode layer. In this case, in order to fulfill the above function, impurity elements must be introduced into the polycrystalline silicon film, using ion implantation technique. However, there exists the upper limit in the concentration of impurities such as donor or acceptor introduced into the polycrystalline silicon film. From the above reasons, it can be seen that it is difficult to eliminate the depletion of the gate electrode layer when forming the gate electrode layer using the polycrystalline silicon film. On the contrary, metals are used as the material of the gate electrode layer, what is called, the technical development of MOSFET including a metal gate electrode layer has been made. In such MOSFET, the entirety of the gate electrode layer or the gate electrode layer interface contacting with the gate insulating film is formed of refractory metal materials, i.e., metal materials having a high melting-point. By doing so, it is possible to eliminate the depletion of the gate electrode layer.
If the gate electrode layer is formed using dry etching technique, it may be formed in the following manner. The principal portion of the gate electrode layer is formed of the polycrystalline silicon film; on the other hand, the gate electrode layer interface contacting with the gate insulating film is formed of refractory metal materials. In this case, the polycrystalline silicon film can be readily and accurately formed into a gate electrode layer pattern using the conventional dry etching technique.
The manufacturing process of semiconductor devices according to the conventional technique will be described below with reference to
FIG. 6
to FIG.
8
. Here, the method of manufacturing CMOS transistors will be described as one example.
FIGS. 6A
to
6
C,
FIGS. 7A
to
7
C and
FIGS. 8A
to
8
C are cross-sectional views in a direction vertical to the lengthwise direction of the gate electrode layer in N-type and P-type MOSFETs.
As shown in
FIG. 6A
, a shallow trench isolation region
201
is formed on a silicon substrate
200
with a predetermined interval using known STI (Shallow Trench Isolation) technique. Thereafter, an aluminum oxide film (Al
2
O
3
film)
202
and a titanium nitride film
203
are successively formed.
Each interval between the isolation regions
201
is used as a device forming region where a semiconductor device such as N-type or P-type MOS transistor is formed. In the present example, as seen from
FIG. 6A
, the left side is an N-type MOSFET region; on the other hand, the right side is a P-type MOSFET region.
The aluminum oxide film (Al
2
O
3
film)
202
is used as the material for forming the gate insulating film of the N-type and P-type MOSFETs so as to have a thickness of about 2 nm. In addition, the refractory metal material, that is, the titanium nitride film
203
is used as part of the gate electrode layer so as to have a thickness of about 10 nm.
As depicted in
FIG. 6B
, a photo resist film
204
is formed so as to cover the N-type MOSFET region using lithography technique. Thereafter, wet etching is carried out using the photo resist film
204
as a mask so that the titanium nitride film
203
existing on the P-type MOSFET region can be removed. In this case, hydrogen peroxide water (H
2
O
2
) is used for the wet etching process so that the titanium nitride film
203
existing on the P-type MOSFET region can be removed.
As described above, the titanium nitride film
203
existing on the P-type MOSFET region is removed by the above wet etching process. Thereafter, the aluminum oxide film (Al
2
O
3
)
202
(gate insulating film) on the P-type MOSFET region is directly exposed to a processing solution, and then, the surface is non-uniformly etched by the processing solution. For this reason, flatness reduces in the surface of the aluminum oxide film (Al
2
O
3
)
202
; as a result, reliability as gate insulating film also reduces.
A mixed solution of sulfuric acid and hydrogen peroxide water is used so that the photo resist film
204
can be removed. Thereafter, as illustrated in
FIG. 6C
, a tungsten nitride film
205
is formed as a refractory metal film on the N-type and P-type MOSFET regions so as to have a thickness of about 10 nm. Next, a polycrystalline silicon film
206
is formed over the entire surface of the above tungsten film by CND process. In this case, the polycrystalline silicon film
206
is formed in a state of containing impurities such as phosphorus (P).
In the N-type MOSFET region, the tungsten nitride film
205
is formed on the titanium nitride film
203
in the multi-layer form. In the P-type MOSFET region, the tungsten nitride film
205
is used as the material for forming a metal gate layer.
Heat treatment (anneal process) of about 800° C. is carried out so that impurities (e.g., phosphorus (P)) contained in the polycrystalline silicon film
206
can be activated. Thereafter, as shown in
FIG. 7A
to
FIG. 7C
, a gate electrode layer pattern will be formed on each of the N-type and P-type MOSFET regions using lithography and dry etching techniques.
First, as illustrated in
FIG. 7A
, in each of the N-type and P-type MOSFET regions, a gate electrode layer pattern is formed on polycrystalline silicon film
206
using a photo resist pattern
207
as a mask. More specifically, in each of the N-type and P-type MOSFET regions, the photo resist pattern
207
having a dimension and shape of the gate electrode layer is simultaneously formed on the polycrystalline silicon film
206
using lithography techniques. Thereafter, the photo resist film
207
is used as a mask, and then, a gate electrode layer pattern is transferred to the polycrystalline silicon film
206
using dry etching technique such as reactive ion etching (hereinafter, referred to as RIE).
As seen from
FIG. 7B
, in each of the N-type and P-type MOSFET regions, with the use of the polycrystalline silicon film
206
, the tungsten nitride film
205
is simultaneously etched into a predetermined dimension and shape using dry etching technique. In this case, RIE process is employed as the dry etching technique.
As shown in
FIG. 7C
, in the N-type MOSFET region, with the use of a multi-layer pattern of the polycrystalline silicon film
206
and the tungsten nitride film
205
as a mask, the titanium nitride film
203
is etched into a predetermined dimension and shape using dry etching technique. In this case, RIE process is employed as the dry etching technique.
Erdem Fazli
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Flynn Nathan J.
Kabushiki Kaisha Toshiba
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