Semiconductor memory array of floating gate memory cells...

Details Semiconductor memory array of floating gate memory cells... Semiconductor memory array of floating gate memory cells...

2002-06-25

2004-06-29

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S316000, C257S321000

Reexamination Certificate

active

06756633

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a self-aligned method of forming a semiconductor memory array of floating gate memory cells. The present invention also relates to a semiconductor memory array of floating gate memory cells of the foregoing type.
BACKGROUND OF THE INVENTION
Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type.
One of the problems facing the manufacturability of semiconductor floating gate memory cell arrays has been the alignment of the various components such as source, drain, control gate, and floating gate. As the design rule-of integration of semiconductor processing decreases, reducing the smallest lithographic feature, the need for precise alignment becomes more critical. Alignment of various parts also determines the yield of the manufacturing of the semiconductor products.
Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more steps involving one or more materials such that the features are automatically aligned with respect to one another in that step processing. Accordingly, the present invention uses the technique of self-alignment to achieve the manufacturing of a semiconductor memory array of the floating gate memory cell type.
There is a constant need to shrink the size of the memory cell arrays in order to maximize the number of memory cells on a single wafer. It is well known that forming memory cells in pairs, with each pair sharing a single source region, and with adjacent pairs of cells sharing a common drain region, reduces the size of the memory cell array. However, a large area of the array is typically reserved for the bit-line connection to the drain regions. The bit-line area is often occupied by the contact openings between memory cell pairs, and the contact to wordline spacing (which strongly depends upon lithography generation), contact alignment and contact integrity. In addition, significant space is reserved for the word-line transistor, the size of which is set by lithography generation and junction scaling.
Another aspect addressed by the present invention involves the erase performance of the memory cell.
FIG. 1
illustrates a well known non-volatile memory cell design, which includes a floating gate
1
disposed over and insulated from a semiconductor substrate
2
having source and drain regions
3
/
4
. A control gate
5
has a first portion that is disposed laterally adjacent to the floating gate
1
, and a second portion that is disposed vertically over and overlapping the floating gate
1
. The floating gate
1
includes a relatively sharp edge
6
that extends upwardly toward the control gate second portion. The edge
6
extending toward the overlapping portion of the control gate
5
enhances Fowler-Nordheim tunneling used to erase the memory cell. As the cell size is scaled down, at least some of the overlap between control gate
5
and floating gate
1
must be maintained so that the upwardly oriented pointed edges can be used for the erase function. This cell architecture imposes a scaling limit on the erase coupling ratio due to the finite overlap capacitance between the control gate
5
and the floating gate
1
.
There is a need for a non-volatile, floating gate type memory cell array with significant cell size reduction without adversely compromising the erase coupling ratio of the memory cell.
SUMMARY OF THE INVENTION
The present invention solves the above mentioned problems by providing a self aligned method of forming memory cells with reduced size, by minimizing the space needed for the bit-line connection and word-line transistor and eliminating the need for a vertical overlap between the control gate and floating gate, and a memory cell array formed thereby.
The present invention is an electrically programmable and erasable memory device that includes a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions formed in the substrate and having a second conductivity type with a channel region of the substrate defined therebetween, an electrically conductive floating gate disposed over and insulated from at least a portion of the channel region, wherein the floating gate includes a horizontally oriented edge extending from a lateral side of the floating gate, and an electrically conductive control gate having at least a portion thereof disposed laterally adjacent to and insulated from the horizontally oriented edge.
In another aspect of the present invention, and array of electrically programmable and erasable memory devices includes a substrate of semiconductor material of a first conductivity type, and spaced apart isolation regions formed on the substrate which are generally parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions. Each of the active regions includes a plurality of memory cells, where each of the memory cells includes first and second spaced-apart regions formed in the substrate having a second conductivity type with a channel region of the substrate defined therebetween, an electrically conductive floating gate disposed over and insulated from at least a portion of the channel region wherein the floating gate includes a horizontally oriented edge extending from a lateral side of the floating gate, and an electrically conductive control gate having at least a portion thereof disposed laterally adjacent to and insulated from the horizontally oriented edge.
In yet another aspect of the present invention, a method of forming a semiconductor memory cell includes the steps of forming first and second spaced apart regions in a semiconductor substrate having a conductivity type different from that of the substrate, wherein a channel region of the substrate is defined between the first and second regions, forming a floating gate of electrically conductive material disposed over and insulated from at least a portion of the channel region, wherein the floating gate includes a horizontally oriented edge extending from a lateral side of the floating gate, and forming a control gate of electrically conductive material having at least a portion thereof disposed laterally adjacent to and insulated from the horizontally oriented edge.
In still yet another aspect of the present invention, a method of forming an array of semiconductor memory cells includes the steps of forming spaced apart isolation regions on the substrate having a first conductivity type which are generally parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions, forming a plurality of spaced apart first and second regions in the semiconductor substrate having a second conductivity type, wherein a plurality of channel regions in the active regions of the substrate are defined each extending between one of the first regions and one of the second regions, forming a plurality of floating gates of electrically conductive material each disposed over and insulated from at least a portion of one of the channel regions, wherein each of the floating gates includes a horizontally oriented edge extending from a lateral side of the floating gate, and forming a plurality of electrically conductive control gates each having at least a portion thereof disposed laterally adjacent to and insulated from one of the horizontally oriented edges.
In even another aspect of present invention, a method of operating an electrically programmable and erasable memory device having an electrically conductive floating gate disposed over and insulated from a substrate of semiconductor material, and an electrically conductive control gate having at least a portion thereof disposed laterally adjacent to the floating gate and insulated therefrom by an insulating material, includes the

Affiliated with

Also associated with

Rating

Semiconductor memory array of floating gate memory cells... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory array of floating gate memory cells..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory array of floating gate memory cells... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3304761