Static information storage and retrieval – Powering – Conservation of power
Reexamination Certificate
2002-12-31
2004-11-16
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Powering
Conservation of power
C365S226000, C365S189110
Reexamination Certificate
active
06819621
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor devices, and more particularly relates to methods and apparatuses for reducing power consumption of semiconductor devices.
BACKGROUND OF THE INVENTION
The field of semiconductor memory devices generally and complementary metal-oxide semiconductor (CMOS) devices in particular is enormously active and rapidly developing. Various categories and sub-categories of semiconductor devices are known and commercially available. The ever-increasing popularity and ubiquity of computers and computer-based devices, both in the consumer and industrial realms, is such that the demand for semiconductor memory devices of a variety of different types will continue to grow for the foreseeable future.
In the field of semiconductor fabrication, a persistent issue has been that of current leakage through thin dielectric layers. Those of ordinary skill in the art will appreciate that leakage through the gate dielectrics of field-effect transistors (FETs) is common referred to Fowler-Nordheim tunneling, whereas gate-induced diode leakage (GIDL) occurs at the edge of gate electrode. (This phenomenon is also interchangeably referred to as gate-induced drain leakage.) It is believed that any transistor having a gate overlying source or drain diffusion region to at least some extent is susceptible to GIDL. As gate dielectrics, which are typically formed of silicon oxide, become increasingly thinner due to continued scaling of semiconductor structures in pursuit of faster and more efficient operation, problems relating to GIDL present an ongoing challenge to circuit designers.
GIDL results from the generation of electron-hole pairs in the surface of the depletion region of a FET along the area where the gate conductor overlies the drain diffusion region (separated by a dielectric layer) when the device is biased such that the drain potential is greater than the gate potential (for NMOS devices) or lower than the gate potential (for PMOS devices).
FIG. 1
is a side cross-sectional illustration of a portion of a FET
10
including a gate conductor
12
and a drain diffusion region
14
formed on a silicon substrate
16
. As shown in
FIG. 1
, it is often the case that a portion of the drain diffusion region
14
of a FET is positioned under the gate conductor
12
. As a result, for an NMOS device, if the gate conductor
12
is at 0 volts and the drain diffusion region
14
is at a positive voltage, there is volume
18
of carrier generation due to the electric field induced by the drain-to-gate voltage differential &Dgr;V
GIDL
. Such carrier generation tends to impair device performance. In addition to increasing standby power, in the context of dynamic random access memory devices, GIDL can degrade data retention time, such that the maximum time between refreshes of a memory array is undesirably decreased.
Various approaches have been proposed in the prior art for overcoming GIDL phenomena in semiconductor devices. Prominent among these are strategies for either increasing the thickness of the gate oxide in a FET, or for otherwise making the gate oxide more resistant to leakage current; various doping strategies for minimizing GIDL effects have also been proposed. Various approaches are proposed, for example, in U.S. Pat. No. 6,294,421 to Gonzalez et al., entitled “Method of Fabricating Dual-Gate Dielectric;” in U.S. Pat. No. 6,097,070 to Mandelman et al, entitled “MOSFET Structure and Process for Low Gate Induced Drain Leakage (GILD) [sic];” in U.S. Pat. No. 6,090,671 to Balasubramanyam et al., entitled “Reduction of Gate-Induced Drain Leakage in Semiconductor Devices;” and U.S. Pat. No. 6,297,105 to Guo, entitled “Method of Forming Asymmetric Source/Drain for a DRAM Cell.” Each of the foregoing patents is hereby incorporated by reference herein in its entirety.
Despite semiconductor designers' ongoing efforts to stabilize and minimize the power consumption of semiconductors and in particular to minimize the undesirable phenomenon of GIDL, there nevertheless continues to be an ongoing need for improvements in the field. Among other considerations, the various proposed strategies for alleviating GIDL phenomenon in semiconductor devices often suffer to greater or lesser extents from the disadvantages of unduly increasing device size, adding complexity to the fabrication process, or degrading device performance.
SUMMARY OF THE INVENTION
In view of the foregoing considerations, the present invention is directed to a method and apparatus for reducing the effects of GIDL in semiconductor devices.
In one embodiment of the invention, the invention is applied to word line driver circuitry in a semiconductor memory device, and entails providing circuitry for locally reducing the supply voltage to elements of the word line driver circuitry during selected periods of device operation.
In accordance with one aspect of the invention, a local power supply node in a semiconductor device is selectively coupled to a supply potential by means of one or more decoupling transistors. The decoupling transistor(s) is/are controlled by means of one or more control signals to interrupt the direct coupling of the local power supply node to the supply potential only during selected operational events, thereby locally reducing the voltage supplied to elements susceptible to GIDL.
In accordance with another aspect of the invention, a “global” power supply signal (i.e., a signal provided to various functional elements throughout an integrated circuit), is coupled to a local power supply node by means of one or more decoupling transistors, as well as by a vt-connected transistor. When the one or more decoupling transistors are off, the voltage on the local power supply node is prevented from exceeding approximately one transistor threshold voltage (vt; approximately 0.6- to 0.7-volts) less than the global power supply signal level. The reduced voltage on the local power supply node lessens the GIDL current in the GIDL-susceptible elements, including P-channel transistors, coupled the local power supply node.
In accordance with another aspect of the invention the one or more decoupling transistors are switched on in advance of a word line driving operation, such that the voltage on the local power supply node is raised to the level of the global power supply signal during word line drives.
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Koelling Jeff
Morris Jon
Omer Rishad
Schreck John
Micro)n Technology, Inc.
Nguyen Tan T.
Wong Cabello Lutsch Rutherford & Brucculeri LLP
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