Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Polycrystalline semiconductor
Reexamination Certificate
2002-12-20
2004-06-01
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Polycrystalline semiconductor
C438S413000
Reexamination Certificate
active
06743701
ABSTRACT:
BACKGROUND
The present invention generally relates to a method of isolating transistor areas. Currently, transistor areas are isolated using shallow trench isolation (STI) methods. STI methods, which are used in the beginning of the integrated circuit wafer fabrication process, have become complicated and expensive.
In addition to the complicated and expensive fabrication processes, the signal delay in current transistor architecture is due to coupling the source-drain region to the silicon substrate. Also, the dynamic portion of the ever-increasing power consumption of logic designs is directly dependent upon the source-drain coupling capacitance. The silicon on insulator process (SOI) is being investigated as a solution to the delay and power consumption issue. However, SOI adds additional expense and complication to the process and design. Some problems experienced with SOI include differential biasing of the junctions, self heating of the junctions, additional contact to the source-drain areas and ESD protection for the design.
A currently used method, based on STI process, of completing the steps to isolate one active area from another area is shown in
FIGS. 1
a
-
1
g
. The process begins as shown in
FIG. 1
by providing a silicon wafer
10
with an initial oxide layer
12
, and a nitride layer
14
. Next, as shown in
FIG. 1
b
a resist layer
16
with a masked opening
18
is provided on the nitride layer
14
. As shown in
FIG. 1
c
, an etching process is then used to cut through the nitride layer
14
and the oxide layer
12
to form a trench
20
in the wafer
10
. The resist layer
16
is then removed and the resultant wafer
22
is shown in
FIG. 1
d.
An oxide layer
24
is then deposited over the resultant wafer
22
to fill the trench
20
as shown in
FIG. 1
e
. Next a chemical mechanical polishing (CMP) step is performed to remove the excess oxide layer
24
.
FIG. 1
f
shows the wafer after a CMP step has been performed with a resultant dishing
26
in the oxide island
24
that filled trench
20
. The final oxide island
28
is shown in
FIG. 1
g
. As shown in
FIG. 1
g
the initial oxide layer
12
and the nitride layer
14
have been removed. The wafer
10
includes bare silicon or active areas
30
.
Other methods of isolating active areas include older methods such as, for example, LOCOS or diode junctions. Generally speaking, STI is used today because the LOCOS process is incapable of oxidizing the exposed silicon in small areas at the same rate as in large areas. This produces variations in the resultant well resistance. The STI process, however, includes many steps, is costly and it prone to process problems. For example, often problems are experienced with controlling the angle of the etched side walls as the pattern density changes across the die resulting in variations in the size of the transistors. Likewise, the oxide removal rate changes relating to the pattern density leaving behind unwanted topography. In addition, as the process geometries shrink, the aspect ratio increases causing problems with trench filling using the HDP method.
OBJECTS AND SUMMARY
A general object of an embodiment of the present invention is to provide a method for forming an active area in a wafer by utilizing reverse trench isolation.
Another object of an embodiment of the present invention is to provide a method for forming an active area in a wafer with smaller geometries.
Yet another object of an embodiment of the present invention is to provide a less expensive method for forming an active area in a wafer.
Yet another object of an embodiment of the present invention is to provide a less complicated method for forming an active area in a wafer.
A further object of an embodiment of the present invention is to provide a method for forming an active area in a wafer.
A further object of an embodiment of the present invention is to provide a method for forming active areas in a wafer, wherein the small tightly packed transistor regions can be formed.
Another object of an embodiment of the present invention is to reduce the interconnect coupling capacitance for passive devices or interconnect lines due to the lack of use of dummy islands for STI CMP planarization control.
Briefly, and in accordance with at least one of the forgoing objects, an embodiment of the present invention provides a method for forming active areas on a wafer which is less expensive and more robust relative to the currently used standard industry processes.
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Allman Derryl
Berman Michael J.
Reder Steven E.
Owens Beth E.
Trexler, Bushnell, Giangiorgi & Blackstone, LTD
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