Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2001-08-03
2004-12-28
Dang, Khanh (Department: 2112)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S309000
Reexamination Certificate
active
06836812
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a sequencing method for accessing data. More particularly, the present invention relates to a sequencing method for a plurality of master controllers to access a shared resource through a high-speed data bus.
2. Description of Related Art
To access a shared system resource (for example, system memory), master controllers normally rely on a conventional bus such as a PCI bus.
FIG. 1
is a schematic diagram showing a conventional system that permits the access of shared data in a system memory by a plurality of master controllers. As shown in
FIG. 1
, a central processing unit
10
is coupled to a PCI bus
14
through a chipset
12
. The PCI bus
14
provides a 32-bit, 33 MHz accessing speed. The PCI bus
14
is also coupled to a plurality of PCI bus compatible master controllers
16
(PCI bus compatible peripheral devices). Each master controller is capable of asserting a request (REQ) signal to request the use of the PCI bus
14
. An arbiter inside the chipset
12
arbitrates between incoming requests and asserts grant (GNT) signals to master controllers permitting the use of the PCI bus
14
when appropriate. A master controller receiving full control of the PCI bus
14
may access system memory
11
with the help of the chipset
12
. In addition, the system also includes a graphic accelerator
13
connected to an accelerated graphics port (AGP) bus
18
having a 64-bit, 66 MHz accessing speed for rapid display of image data on a display device.
However, most server systems do not require a graphic accelerator for rapid transmission of image data and so most display devices use a PCI bus compatible interface to serve as display devices for showing image data. Consequently, the AGP bus is frequently not fully utilized in the server system. Nonetheless, if the powerful potential of an AGP bus can somehow be tapped so that data is transmitted to the master controllers via the PCI bus rapidly, both resource and system utilization will be increased.
Moreover, a conventional chipset services any request from the PCI bus according to a first-come first-serve principle. Furthermore, data transmission is usually conducted in the same bus transaction cycle immediately after asserting the request. Hence, waiting cycles are needed just to secure the required data. In addition, this arrangement is unable to meet the transmission demands of requests having a higher access priority. Current high-speed bus such as the AGP bus employs a method that treats an access request and a data access separately. A hierarchical pipeline memory write and read operation is also employed to provide high-speed and efficient data transmission. Because each access request has a priority attribute, control chipset must be able to deal with top priority access operations first. The high-speed bus must also include flush and fence signals to ensure proper sequencing of the access operations. However, for a system having a multiple of master controllers all trying to tap into a shared system resource through the high-speed bus, sequencing of requests becomes a big issue.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a sequencing method such that the requests for accessing a shared system resource from a multiple of master controllers are prioritized.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a sequencing method for prioritizing requests from a multiple of master controller. First, a transaction identification value is provided for each transaction so that the performance of each transaction is ordered. A master identification value is also provided for each transaction to serve as a label for identifying the initiating master controller. Finally, transactions having identical master identification value are collected and the transactions are prioritized according to their transaction identification value.
This invention also provides a bridging system for accessing a shared system resource. The bridging system includes a plurality of master controllers, a first bus, a bridging device, a second bus and a chipset. Each master controller is capable of submitting a multiple of write transactions and a multiple of read transactions. The first bus is coupled to the master controllers. The bridging device is coupled to the first bus for re-directing reading transactions or writing transactions. The second bus is coupled to the bridging device. The chipset is coupled to the second bus and the shared system resource for picking up a reading transaction or a writing transaction submitted by a specified master controller and accessing the corresponding shared system resource.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6499079 (2002-12-01), Gulick
patent: 2002/0138790 (2002-09-01), Nishtala
Sartori G, “Hypertransport technology: A high bandwidth, low complexity bus architecture”, Windows Hardware Engineering Conference, Mar. 2, 2001 (http://www.microsoft.com/whdc/winhec/download/HyperTransport.doc).
Dang Khanh
J.C. Patents
Knoll Clifford
Via Technologies Inc.
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