Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-10
2004-12-21
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S335000, C257S336000, C257S337000, C257S338000, C257S339000, C257S340000, C257S341000, C257S342000
Reexamination Certificate
active
06833585
ABSTRACT:
REFERENCE TO RELATED APPLICATIONS
This application claims priority of Korean patent application Serial No. 01-20168, filed Apr. 16, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power semiconductor device, and more particularly, to a high voltage lateral Double diffused Metal Oxide Semiconductor (DMOS) transistor having low on-resistance and high breakdown voltage.
2. Description of the Related Art
Integrated circuits in which a control function and a driver function are combined are usually referred to as smart power devices. Such a smart power device has a lateral DMOS transistor at its output terminal which is designed to usually operate with high voltage. In such a high voltage lateral DMOS transistor, breakdown voltage is critical in terms of the stability of a device, and on-resistance is critical in terms of the operational characteristics of the device. In order to decrease the on-resistance of the device, the doping concentration within a drift region between a drain region and a channel region should be increased. However, in this case, the drift region is not completely depleted resulting in a decrease in breakdown voltage. To overcome this problem, recently, lateral DMOS transistors employing a double Reduced Surface Field (RESURF) structure have been developed. A lateral DMOS transistor employing the double RESURF structure is disclosed in U.S. Pat. No. 6,087,232.
FIG. 1
is a layout diagram of an example of a conventional high voltage lateral DMOS transistor employing the double RESURF structure.
FIG. 2
is a cross-section of the high voltage lateral DMOS transistor of
FIG. 1
, taken along the line II—II.
Referring to
FIGS. 1 and 2
, a p
−
well region
11
and an n-well region
12
are formed in the upper portion of a p-type semiconductor substrate
10
. A p-body region
13
having a channel region on its surface and a deep p
+
region
14
surrounded by the p-body region
13
are formed in the upper portion of the p
−
well region
11
. An n
+
source region
15
and a p
+
contact region
16
surrounded by the n-source region
15
are formed in the upper portion of the p-body region
13
including its surface. The channel region is formed in the upper portion of the p-body region
13
, that is, between the n
+
source region
15
and the n-well region
12
. A p-top region
17
and an n
+
drain region
18
are formed in the upper portion of the n-well region
12
at a predetermined distance from each other.
A gate insulation layer
19
and a gate electrode
20
are sequentially formed on the channel region of the p-body region
13
. The n
+
source region
15
and the p
+
contact region
16
are electrically connected to a source electrode
21
. The n
+
drain region
18
is electrically connected to a drain electrode
22
. The gate electrode
20
, the source electrode
21
and the drain electrode
22
are insulated from one another by an interlayer insulation layer
23
. Reference numeral
24
denotes an isolation layer.
In such a lateral DMOS transistor, when a bias voltage is applied to the n
+
drain region
18
, a reverse bias voltage is applied to a first junction J
1
between the semiconductor substrate
10
and the n-well region
12
, and to a second junction J
2
between the p-top region
17
and the n-well region
12
. Here, a depletion region is vertically formed around the first and second junctions J
1
and J
2
. Particularly, since a depletion region in the n-well region
12
is formed out of not only the first junction J
1
but also the second junction J
2
, the n-well region
12
is completely depleted. When the n-well region
12
is completely depleted, a surface electric field is uniformly formed between the n
+
source region
15
and the n
+
drain region
18
so that the breakdown voltage of the device increases.
However, the on-resistance of the device may increase due to the p-top region
17
. In addition, an area, in which carriers move, between the n~ source region
15
and the n
+
drain region
18
is reduced so that the current carrying performance of the device is reduced.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a high voltage lateral Double diffused Metal Oxide Semiconductor (DMOS) transistor having low on-resistance and high breakdown voltage without reducing current carrying performance between a source and a drain.
Accordingly, to achieve the above object of the invention, there is provided a high voltage lateral DMOS transistor including a semiconductor substrate of a first conductivity type. A gate electrode is partially formed on the semiconductor substrate to be insulated from the semiconductor substrate. A body region of the first conductivity type with a channel region overlapping with the gate electrode is formed in a first area of the semiconductor substrate. A source region of a second conductivity type is formed within the body region. A drift region of the second conductivity type is formed in a second area of the semiconductor substrate adjacent to the channel region. A drain region of the second conductivity type is formed within the drift region. Pluralities of well regions of the first conductivity type are formed to be horizontally spaced out within the drift region.
Preferably, each of the well regions of the first conductivity type has the shape of a column, the top surfaces of the well regions and the top surface of the drift region are on the same plane, and the bottom surfaces of the well regions and the bottom surface of the drift region are on the same plane. Preferably, each of the top and bottom surfaces of each well region of the first conductivity type having the shape of a column has a circular shape. Preferably, the well regions of the first conductivity type are disposed between the channel region and the drain region. Preferably, the high voltage lateral DMOS transistor further includes a source electrode electrically connected to the source region, and a drain electrode electrically connected to the drain region. Preferably, the first conductivity type is a p-type, and the second conductivity type is an n-type. Alternatively, the first conductivity type may be an n-type, and the second conductivity type may be a p-type.
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Choi Young-suk
Jeon Chang-ki
Kim Min-hwan
Fairchild Korea Semiconductor
FitzGerald Esq. Thomas R.
Roach, Esq. Laurence S.
Soward Ida M.
Zarabian Amir
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