Stable PD-SOI devices and methods

Details Stable PD-SOI devices and methods Stable PD-SOI devices and methods

2002-07-18

2004-12-07

Elms, Richard (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S288000, C257S348000, C257S349000, C257S616000

Reexamination Certificate

active

06828632

ABSTRACT:

TECHNICAL FIELD
This disclosure relates generally to integrated circuits, and more particularly, to partially depleted silicon-on-insulator systems, methods and devices.
BACKGROUND
PD (partially depleted)-SOI (silicon-on-insulator)-CMOS (complementary metal oxide semiconductor) technology has significant speed, power and radiation immunity advantages over bulk CMOS technology. However, it has been difficult to manage the floating body effect (FBE) of SOI devices. One problem associated with PD-SOI-CMOS devices involves an unstable body potential over a range of frequencies. Thus, PD-SOI-CMOS technology has yet to be widely accepted by the systems and design communities.
In bulk NMOSFET devices, for example, the body often is tied to a fixed potential or to the source of the device However, the body potential in NMOSFET-SOI is floating and remains unstable due to the complex dynamics of hole generation at the drain edge, and with carrier recombination and diffusion. Several undesirable characteristics results from FBE, such as “Kink Effect” (current enhancement) in Id-Vg characteristics of the device, enhanced leakage due to parasitic (npn) bipolar (BJT) current, and enhanced 1/f noise. These effects restrict the ability to design complex circuits and the range of applications for SOI technology. Circuit-related issues attributable to FBE include threshold instability, hysteretic behavior in signal input/output, frequency-dependent pulse delays, and signal pulse width modulation.
In logic design, FBE can lead to data loss, dynamic circuit failure and timing delays. Additionally, FBE can limit analog circuit applications due to transistor mismatch and enhanced AC/DC noise.
One proposed solution for suppressing FBE involves Field Shield Isolation technology. Another proposed solution for suppressing FBE involves Bipolar Embedded Source Structure (BESS). Another proposed solution for suppressing FBE involves Si—Ge Inserted SOI. Another proposed solution for suppressing FBE involves SOI devices with implanted recombination centers. Another proposed solution involves Schottky body-contacted SOI.
These proposed solutions reduce parasitic effects by regulating body potential but do not provide frequency independent device threshold. Therefore, these proposed solutions are limited in scope since the floating body potential is time dependent and the body potential at any instant is the transient result of multiple mechanisms of widely differing time constants. If the body potential could be regulated such that it is time-independent (i.e. frequency independent), and could be accurately predicted, the body potential could be utilized to significantly enhance circuit performance and complex circuit design.
Additionally, in the current state-of-the-art associated with bulk silicon technology, complex circuit and system designs require the use of design simulators, tools, and methodology in which embedded device models accurately predict device thresholds within a wide range of operating frequencies at all design and application conditions (viz. geometry, doping profile, temperature, node potential etc). However, these simulators, tools and methodology are not available for SOI technology due to the time-dependent threshold of the floating body SOI device.
Therefore, there is a need in the art to provide improved PD-SOI-CMOS devices and fabrication methods that ensures frequency-independent device threshold by means of providing frequency independent body potential.
SUMMARY
The above mentioned problems are addressed by the present subject matter and will be understood by reading and studying the following specification. The present subject mater provides a PD-SOI-CMOS device and fabrication method that achieve a stable body potential over a wide frequency range spanning from the steady state to the fastest transient. Thus, the PD-SOI-CMOS devices are able to be used for enhanced device and circuit performance. The PD-SOI-CMOS device provides a stable device threshold independent of circuit switching frequency as long as the stable body potential value is appropriately lower than the built-in potential of the body-source (NFET) junction. The device is immune to parasitic FBE. Complex and wide range of static and dynamic circuits are capable of using such devices and standard design tools, including system on chip solutions and other complex chip designs.
One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. According to various embodiments, the structure includes a substrate, an oxide insulation layer disposed above the silicon substrate, and a well region formed above the oxide insulation layer. In various embodiments, the well region includes a first silicon (Si) epitaxial layer disposed above the oxide insulation layer, a silicon germanium (Si—Ge) epitaxial layer disposed above the first Si epitaxial layer, and a second Si epitaxial layer disposed above the Si—Ge epitaxial layer. In various embodiments, the first Si epitaxial layer includes a number of recombination centers. These recombination centers are also referred to herein as BOX (buried oxide) recombination centers as they are in the proximity of the buried oxide region of the device. In various embodiments, the Si—Ge epitaxial layer includes a number of recombination centers. At least one source region and at least one drain region are formed in the well region. In various embodiments, the recombination centers in the Si—Ge epitaxial layer are positioned selectively in only the source region or both in the source and drain regions. A gate oxide layer is formed above the well region to define a channel region in the well region between the source region and the drain region. A gate is formed above the gate oxide layer. In various embodiments, a metal silicide layer is formed above the source-drain region as well as on top of the polysilicon gate, and a second lateral metal Schottky layer with appropriate work function is selectively formed above the source region and the substrate region.
The selectively formed lateral metal Schottky layer provides an integrated source-body Schottky diode whose forward characteristics uniquely targets the steady state potential for the body of the SOI device. In various embodiments, the steady state potential for the body of the SOI device is capable of being targeted in the range of 0.3 to 0.5 volts, depending on the material work function used for the lateral metal Schottky layer. The body does not get sufficiently charged up to trigger the bipolar action because the body has and maintains a low, stable potential that is lower than the source-substrate forward potential required for bipolar action.
The graded, epitaxially grown Si—Ge layer creates a lower body-source barrier potential and provides a preferential path for sweeping thermally-generated excess holes for recombination at the source-body region of the channel associated with that region. The localized recombination centers in the Si—Ge epitaxial layer enhance of the recombination of holes at the source-body region of the channel.
The BOX recombination centers readily recombine excess holes generated by impact ionization at the bottom part of the drain-body region. These excess holes are recombined at the body-BOX region. This recombination of excess holes has a very short time constant because of the proximity of the recombination centers.
Regardless of the time constant and mechanism of hole generation, the recombination time constant is significantly faster than the intrinsic switching time of the device, and therefore, the threshold of the device is maintained constant at all circuit frequencies. The resulting device does not exhibit any floating body parasitic effects or any enhanced DIBL (drain induced barrier lowering) effect as seen in standard SOI devices. Circuits do not exhibit hysteretic effects, regardless of pulse frequency. Additionally, circuits do not exhibit excessive pass-gate leakage induced data loss or pulse width modulation. The lower threshold for such device w

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