Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2003-05-07
2004-12-14
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C710S108000
Reexamination Certificate
active
06832335
ABSTRACT:
TECHNICAL FIELD
The technical field is computer architecture that use mechanisms to prevent conflicting access to shared computer resources.
BACKGROUND
Current computer systems use various means to ensure temporary exclusivity of access of a central processing unit (CPU) or other active system agent to a memory data item or input/output device. One such means is a bus lock. A bus lock is a hardware mechanism in which the agent programmed for atomic, exclusive access to the memory data item, the input/output device, or a combination of the two, signals its requirement for exclusive access using a signal transmitted on to a system bus or interconnect. Other system agents are then prevented from accessing the locked item or items during the interval that the locking agent signals exclusive access.
This hardware bus locking mechanism presents serious performance issues, with a disproportionately larger impact on larger systems. This is because it is generally prohibitively complex to restrict the scope of the lock, using hardware mechanisms, to the particular items being accessed. For example, large portions of a system, or even the entire system, may be inaccessible to other agents during the lock, causing substantial stalls.
Even without trying to narrow the scope of the lock, the implementation of hardware bus lock in large systems is complex. The complexity arises from having to propagate the lock indication through the system, over perhaps many busses or other interconnects, while managing conflicting, simultaneous lock attempts so as to assure forward progress and data integrity. For example, current computer systems may be implemented using several busses, all running in parallel. In such a system, two or more lock attempts may occur simultaneously, and some type of arbitration mechanism would be required to determine which active agent acquires the bus lock. Otherwise, a deadlock situation could arise, and system processing could be halted.
One solution to this problem is to implement the computer system hardware so that no matter how large the computer system, a system-wide bus lock is available. However, this solution is impractical because one process running on one processor in the computer system can cause a system-wide stall during the time the bus lock is being serviced.
Another solution to the above design performance problems is to administer the exclusivity using cacheable semaphores. However, this choice is not directly available in the case of a computer system required to be backward compatible with a legacy architecture that makes the bus lock feature available in a visible way to software.
SUMMARY
What is disclosed is a software emulation module that provides the functions of a hardware bus lock without the attendant disadvantages of the hardware bus lock. Code sequences that would ordinarily trigger a bus lock signal are used to cause a fault. A fault handler acquires a cacheable semaphore that is reserved for bus lock emulation purposes. The fault handler also acquires a semaphore that is used to ensure exclusive access to native page tables or equivalent address space protection mechanisms. The software emulation module then causes invalidation of relevant page table entries, purges translation lookaside buffer pages of the locking accesses, and sets a mode bit that defeats any fault-on-lock-attempt behavior. The emulation module then locally inserts any needed translation/protection entries, executes the locking sequence and then clears the mode bit. Finally, the emulation module causes the semaphores to be released and the normal flow of execution returns.
Using the software emulation module, the portion of memory space that is locked may be reduced, using paging or a similar mechanism, and other system agents are only affected if the agents attempt to access the locked portion of the memory space during the interval in which the bus lock signal is asserted.
Also disclosed is a method for software emulation of hardware bus lock in a computer system. The method begins with a device in the computer system attempting a bus lock operation. The method then includes acquiring a bus lock semaphore, providing the bus lock semaphore to a device attempting the bus lock operation, acquiring a page table semaphore, and invalidating page table entries to prevent access to a location in the computer system referenced by the bus lock operation. The method continues with purging translation lookaside buffer pages associated with the location, inserting local translation entries, and executing a clone instruction without lock semantics.
REFERENCES:
patent: 5050072 (1991-09-01), Earnshaw et al.
patent: 5572734 (1996-11-01), Narad et al.
patent: 5655111 (1997-08-01), Uegaki
patent: 5761659 (1998-06-01), Bertoni
patent: 5850529 (1998-12-01), Nakamura
patent: 5859999 (1999-01-01), Morris et al.
patent: 5860017 (1999-01-01), Sharangpani et al.
patent: 5894562 (1999-04-01), Moyer
patent: 5987550 (1999-11-01), Shagam
patent: 6076126 (2000-06-01), Shagam
patent: 6295598 (2001-09-01), Bertoni et al.
patent: 6430657 (2002-08-01), Mittal et al.
patent: 6574755 (2003-06-01), Seon
Beausoliel Robert
Hewlett--Packard Development Company, L.P.
McCarthy Christopher S.
LandOfFree
Transparent software emulation as an alternative to hardware... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Transparent software emulation as an alternative to hardware..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transparent software emulation as an alternative to hardware... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3299924