Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-11-14
2004-06-29
Tran, Thien F (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S317000, C257S319000, C257S320000, C257S321000
Reexamination Certificate
active
06756631
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a non-volatile semiconductor memory device and its memory array and, more particularly, to method of forming a stacked-gate cell structure and its NAND-type flash memory array.
2. Description of Related Art
A stacked-gate cell structure is one of the basic non-volatile semiconductor memory structure for forming a high-density flash memory array. In general, a stacked-gate cell can be programmed by channel hot-electron injection (CHEI) mechanism through a high drain field near a drain edge and can be erased by Fowler-Nordheim (FN) tunneling mechanism through an overlapping region between the floating-gate and the common-source diffusion region or between the floating-gate and the semiconductor substrate. In general, the programming power is high and the programming efficiency is low for channel hot-electron injection mechanism and the stacked-gate length is difficult to be scaled due to the punch-through effect. The stacked-gate cell structure with the channel hot-electron injection mechanism as a programming method is often implemented as a NOR-type flash memory array.
The stacked-gate cell structure can be programmed and erased by Fowler-Nordheim tunneling mechanism to obtain low power programming and erasing between the floating-gate and the semiconductor substrate. A cross-sectional view of a conventional stacked-gate cell structure in a NAND-type array is shown in
FIG. 1
, in which
FIG. 1A
shows the stacked-gate cell structure in a programming state and
FIG. 1B
shows the stacked-gate cell structure in an erasing state. From FIG.
1
A and
FIG. 1B
, a gate stack comprising from top to bottom a tungsten-disilicide layer
105
, a doped polycrystalline-silicon layer
104
, an intergate-dielectric layer
103
, a doped polycrystalline-silicon layer
102
, and a tunneling-oxide layer
101
is patterned in general with a minimum feature size (F) of technology used and is fabricated on a p-well
100
b
formed within an n-well
100
a
; and symmetrical common-source/drain n
+
diffusion regions
106
a
/
106
b
are formed in a self-aligned manner by implanting a high dose of doping impurities into the p-well
100
b
by using the gate stack as an implantation mask. From
FIG. 1A
, as the control-gate
105
,
104
is applied with a high positive gate voltage (for example +18V), the source/drain n
+
diffusion regions
106
a
/
106
b
, the p-well
100
b
, and the n-well
100
a
are grounded, electrons in the induced surface inversion layer and the source/drain n
+
diffusion regions
106
a
/
106
b
under the tunneling-oxide layer
101
may tunnel across the tunneling-oxide layer
101
into the floating-gate layer
102
for performing a programming operation. From
FIG. 1B
, the control-gate
105
,
104
is grounded, the p-well
100
b
and the n-well
100
a
are applied with a high positive voltage (for example +20V), and the source/drain n
+
diffusion regions
106
a
,
106
b
are floating, electrons stored in the floating-gate layer
102
may tunnel across the tunneling-oxide layer
101
into the p-well
100
b
for performing an erasing operation. It is clearly seen that as the gate length of the stacked-gate cell structure shown in FIG.
1
A and
FIG. 1B
is scaled, the effective area for programming and erasing will be drastically reduced and the programming and erasing speed will be reduced accordingly. Moreover, the applied control-gate voltage for programming and the applied p-well and n-well voltage for erasing are relatively high, and therefore, a floating-gate structure having a high coupling ratio is needed in order to reduce the applied control-gate voltage for programming and the applied p-well and n-well voltage for erasing. A typical example for forming a shallow trench isolation (STI) structure having a non-self-aligned floating-gate layer with a high coupling ratio can be fabricated by two critical masking steps to form a self-aligned STI structure and at least four critical masking steps are needed to form a NAND flash memory array over the self-aligned STI structure.
It is, therefore, a major objective of the present invention to offer a stacked-gate cell structure having a tapered floating-gate structure for a NAND-type flash memory array with larger programming and erasing area as the stacked-gate length is scaled.
It is another objective of the present invention to offer a self-aligned floating-gate structure having a high coupling ratio.
It is a further objective of the present invention to offer method of forming a contactless NAND-type flash memory array with less critical masking steps and smaller unit cell size.
SUMMARY OF THE INVENTION
A stacked-gate cell structure having a tapered floating-gate layer is used to implement a contactless NAND-type flash memory array of the present invention, in which the tapered floating-gate layer not only offers a larger surface area over the tunneling-dielectric layer for programming and erasing without enlarging the control-gate length but also provides the tapered tips to increase the erasing speed. The contactless NAND-type flash memory array of the present invention is fabricated on a shallow-trench-isolation (STI) structure having a self-aligned floating-gate structure, wherein the self-aligned floating-gate structure of the present invention offers a larger coupling ratio with less critical masking steps and a smoothed surface for forming an intergate-dielectric layer in order to alleviate the field emission effect due to the sharp corners of the prior art. The width of the string select lines and the ground select lines of a NAND-type array being defined by a spacer formation technique can be made to be smaller than a minimum feature size of technology used. The conductive gate of the select-gate transistors in each of the string/ground select lines is made to have a one-side tapered floating-gate structure and, therefore, can offer a longer channel length as compared to the width of the string/ground select lines. Each of the common-source conductive bus lines is formed over a first flat bed being alternately formed by a common-source diffusion region and a third raised field-oxide layer, and a lower bus-line resistance and a lower bus-line capacitance with respect to the semiconductor substrate can be easily obtained. Each of the bit-line contacts being formed by a planarized common-drain conductive island is simultaneously patterned with a metal bit-line, so a larger contact area and a higher contact integrity for a scaled contact technology can be easily obtained. The contactless NAND-type flash memory array of the present invention can be fabricated with less critical masking photoresist steps and smaller unit cell size as compared to the prior art.
REFERENCES:
patent: 6465837 (2002-10-01), Wu
Intelligent Sources Development Corp.
Pro-Techtor Inter-national Services
Tran Thien F
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