Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2002-02-15
2004-10-19
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S105000, C365S149000, C365S183000, C365S222000
Reexamination Certificate
active
06807604
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of refreshing a dynamic memory intended for storing variables involved in operations performed by a processor. The invention finds application, for example, in a programmable system dedicated to an application with real-time type constraints, such as a video data processing system.
2. Description of the Related Art
In integrated circuits, processing of signals requires ever greater storage capacity. To increase this storage capacity, embedded memories are often used. There are two types of such memories:
static memories, such as static random access memories (SRAMs).
dynamic memories, such as dynamic random access memories (DRAMs).
Static memories are constructed from flip-flops. When a data item is stored in a static memory, this data item remains stored for as long as the circuit containing the static memory is energized. Dynamic memories store the data in the form of a capacitor charge. On account of leakage currents causing losses of charge, it is necessary for these capacitors to be frequently recharged so as to keep the data in memory. This operation is called the refreshing of a data item, and must be performed, depending on the memories used, approximately every 1 to 10 milliseconds. The duration for which a data item can be kept in memory without requiring refreshing is called the “retention time”, and is specific to the data item considered. However, dynamic memories are used on account of their large storage capacity. Specifically, to store a data bit, a dynamic memory requires a single transistor while a static memory requires from 4 to 6 transistors. For the same storage capacity, a dynamic memory thus appears to be less expensive than a static memory. However, the refreshing of the data required by a dynamic memory introduces a non-negligible latency time, during which a processor cannot have access to the data stored in the memory. Specifically, the refresh is performed systematically on all the data contained in the dynamic memory, which requires a considerable amount of time.
In order to remedy this drawback, U.S. Pat. No. 5,148,546 discloses a method making it possible to dynamically determine the memory addresses of the data to be refreshed, so as to refresh, at a given instant, only the data requiring refreshing. Thus, at this given instant, a large number of data items is accessible to the processor, since these data are not monopolized by the refresh circuit, and this results, averaged over time, in a reduction in the latency time. However, this method requires the installation of a subsystem in the circuit, so as to determine the memory addresses of the data to be refreshed. Furthermore, this method does not allow a large reduction in the latency time, since the dynamic determination of the memory addresses of the data to be refreshed also requires a certain amount of time.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a method making it possible to reduce the latency time due to refreshing in a dynamic memory.
According to the invention, a method of refreshing a dynamic memory as defined in the opening paragraph is characterized in that it comprises the steps:
planning an order and a timing of said operations;
estimating a retention time specific to each variable;
forecasting at least one instant at which each variable must be refreshed, an instant at which a given variable must be refreshed being defined as a function of the retention time of said given variable and the timing of the operations in which said given variable is involved;
placing said variables are placed in said memory; and
refreshing said variables at the instants defined during the forecasting step.
The invention exploits the fact that in certain programmable systems, it is possible to ascertain, when compiling a program defining the operations to be performed by the processor, the order of these operations, the timing of these operations and the variables involved in these operations. Moreover, since the retention time specific to a variable is related to the technology used for the fabrication of the dynamic memory, the estimation of this retention time exhibits no difficulties. Thus, having ascertained the instant at which a variable is created, the instant at which this variable is used in an operation and the retention time for this variable, it is possible to forecast the instant at which this variable must be refreshed. Additionally, by placing the variables judiciously in memory, so that the variables which have to be refreshed at the same instant are located, for example, in one and the same area of the memory, it is possible to decrease the latency time due to the refreshing of the dynamic memory. Furthermore, since the refreshing of a variable can be performed by a reading of this variable by the processor, this method does not require the addition of any refresh circuit, i.e., the processor is able to manage the refreshing of the dynamic memory on its own.
In so far as the steps described hereinabove may be performed by software, the invention also provides for a computer program comprising program code instructions for the execution of the steps of the method described hereinabove when said program is executed on a computer.
REFERENCES:
patent: 5148546 (1992-09-01), Blodgett
patent: 6167484 (2000-12-01), Boyer et al.
Goodman Edward W.
Sparks Donald
Truong Bao
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