MRAM configuration having selection transistors with a large...

Details MRAM configuration having selection transistors with a large... MRAM configuration having selection transistors with a large...

2003-05-13

2004-10-12

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S003000, C365S158000, C365S171000, C365S173000

Reexamination Certificate

active

06803618

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to an MRAM configuration (magnetoresistive random access memory) having a multiplicity of MTJ memory cells (magnetic tunnel junction) which are provided in a matrix-like manner in a memory cell array and are in each case located between bit lines running in a first direction of the memory cell array and plate lines. Digit lines are arranged at a distance from the MTJ memory cells and are aligned to the latter row by row. The digit lines extend in a second direction in the memory cell array. The second direction is essentially perpendicular to the first direction. The MRAM configuration has selection or isolation transistors which are connected to the plate lines. The selection transistors have gate terminals connected to word lines. The source-drain paths of the selection transistors are connected between the plate lines and reference-ground potential.
FIG. 3
shows an MTJ memory cell
1
, which is located between a bit line B and a plate line PL. The MTJ memory cell
1
includes a soft-magnetic layer WML, a tunnel barrier layer TB, and a hard-magnetic layer HML. The orientation of the magnetization of the soft-magnetic layer WML is adjustable, while the orientation of the hard-magnetic layer HML is fixed, as is indicated by a double arrow
2
for the soft-magnetic layer WML and an arrow
3
pointing toward the left in
FIG. 3
for the hard-magnetic layer HML.
Situated below the MTJ memory cell
1
is a digit line D through which a programming current I
h
, which generates a magnetic field H
h
, can be sent. The digit line is electrically insulated from the MTJ memory cell
1
and from the plate line PL. The programming current I
h
interacts with a programming current I
0
, which can flow through the bit line B, and generates a magnetic field H
0
. The direction of at least one of the two programming currents I
h
and I
0
must be reversible.
The plate line PL is connected via a connecting line C to a selection or isolation transistor T, whose gate electrode is connected to a word line WL. The source-drain path of the selection transistor is connected between the connecting line C and the reference-ground potential (ground).
Between the bit line B and the plate line PL, the resistance of the MTJ memory cell
1
is lower in the case of a parallel orientation of the magnetization directions in the soft-magnetic layer WML and the hard-magnetic layer HML than in the case of an antiparallel orientation of the magnetizations. Accordingly, one state with a parallel orientation of the magnetizations can be assessed as a “1”, for example, if the state of an antiparallel orientation of the magnetizations is assigned a value of “0”. It goes without saying that an opposite assessment of the states is also possible.
For writing to the MTJ memory cell
1
, programming currents I
0
and I
h
are sent through the bit line B and the digit line D in directions such that the magnetic fields H
0
and H
h
generated by the currents set the orientation of the magnetization of the soft-magnetic layer WML parallel or antiparallel to the orientation of the magnetization of the hard-magnetic layer HML. During this writing operation, the selection transistor T is switched off so that, for example, in the case of an enhancement-mode n-channel MOS transistor, a potential of 0 V is applied to the gate thereof, that is to say to the word line WL.
FIG. 4
illustrates how the MTJ memory cell
1
of
FIG. 3
is read. For this purpose, the selection transistor T is switched on and a sense current I
s
is sent through the bit line B, the MTJ cell
1
, the plate line PL, the connecting line C and the transistor T. Depending on the magnitude of the current I
s
, which is ascertained at the input of the bit line B, the memory content is assessed as a “1” or a “0”.
FIG. 5
shows a memory cell array with MTJ memory cells
1
configured between bit lines B
1
, B
2
and digit lines D
1
, D
2
and D
3
. Each MTJ memory cell
1
is assigned a selection transistor T and the gates of the selection transistors are connected to one another row by row by word lines W
1
, W
2
and W
3
.
FIG. 6
is a plan view of a memory cell array with digit lines D
1
to D
4
, bit lines B
1
to B
3
and word lines W
1
to W
4
of the type illustrated in FIG.
5
. Here, the illustration merely shows in each case an additional digit line D
4
, an additional bit line B
3
, and an additional word line W
4
. If the smallest feature size that can be achieved with the technology respectively employed is designated by F
2
, then it can be seen from
FIG. 6
that a unit cell covering two bits has an area requirement of 12 F
2
, so that each memory cell has a cell size of 6 F
2
. In this case, the channel width of each selection transistor is given by F, as can be seen from the assignment of the connecting line C leading to a ground diffusion region GD with regard to the respective word lines W
1
to W
4
. The drain zone and the source zone are introduced into the ground diffusion region GD respectively in the region below the individual connecting lines C and on the side of the corresponding word line that is opposite to the respective connecting line C.
An MRAM configuration should be able to be written to and read from as rapidly as possible, that is to say, it should have a small internal resistance.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an MRAM configuration which overcomes the above-mentioned disadvantages of the prior art apparatus of this general type.
In particular, it is an object of the invention to provide an MRAM configuration in which the internal resistance is reduced and in which the least possible area is required for a memory cell. That is to say to reduce the internal resistance in conjunction with an area requirement of at most 6 F
2
.
With the foregoing and other objects in view there is provided, in accordance with the invention, an MRAM configuration having a memory cell array with a plurality of bit lines extending in a first direction, a plurality of digit lines extending in a second direction essentially perpendicular to the first direction, a plurality of plate lines, a plurality of word lines, and a matrix of MTJ memory cells. The MRAM configuration also has a plurality of selection transistors connected to the plurality of plate lines. The plurality of selection transistors has a plurality of gate terminals connected to the plurality of word lines. The plurality of selection transistors has source-drain paths connected between the plurality of plate lines and reference-ground potential. Each of the plurality of digit lines is located at a distance from the MTJ memory cells. The plurality of digit lines are for programming the MTJ memory cells. The plurality of digit lines are assigned to the MTJ memory cells row by row. Each one of the plurality of selection transistors is assigned to a number of the MTJ memory cells to thereby define an effective channel width/bit given by [(2n−1)
]·F. Here, n denotes the number of the MTJ memory cells having the one of the plurality of selection transistors assigned thereto; and F
2
denotes a smallest feature size that can be achieved with a respectively employed technology.
In the case of an MRAM configuration of the type mentioned in the introduction, this object is achieved by virtue of the fact that a selection transistor is in each case assigned to a plurality of MTJ memory cells such that its channel width can be determined by the number of MTJ memory cells allocated to it. In this case, a selection transistor may also be allocated to a multiplicity of memory cells.
In the inventive MRAM configuration, a ground diffusion region is preferably assigned to a respective selection transistor. In this case, the ground diffusion region may extend in a finger-shaped fashion below the respective plate lines or else overall be of an essentially rectangular design.
Finally, in the inventive MRAM configuration, the plate lines and also the connecting l

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