Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-08-20
2004-11-09
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06817002
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method and apparatus for compensating or deskewing signal propagation within a printed circuit board (“PCB”). More particularly, the present invention relates to aligning both the rising and falling edges of the system clock, the control signals and the data input and output separately using signal delay elements.
2. State of the Art
As the complexity and data processing speeds of electronic products continue to increase, the properties of the interconnecting circuitry which connects complex and high-speed integrated circuit devices become more pronounced and must be more carefully analyzed and characterized to ensure reliable circuit performance. This increases the cost of fabricating the devices, particularly with regard to the interconnecting circuitry. The data processing speeds obtainable with advanced high-speed integrated circuit devices often dictate the required characteristics of the interconnecting circuitry, and thus can significantly increase the cost of such devices. Currently, integrated circuit devices may operate with a throughput in gigabits per second resulting in pulse durations of less than a nanosecond and rise times in the picosecond range. Under these conditions, even the conductors connecting components within these devices effectively become active components in the circuits, both in terms of affecting propagation delays and impedance matching. Logic circuits are not capable of high-speed circuit operations unless the effects of signal transmission propagation delay are somehow controlled.
Propagation delays are affected by interconnecting circuitry such as printed circuit boards and assemblies, principally as a result of the dielectric constant (&egr;
r
) of the materials used in the circuitry. In particular, materials having low dielectric constants are desirable as they minimize propagation delays and thereby increase the range of obtainable signal speeds within a circuit.
Impedance, which is also a function of the dielectric constant (&egr;
r
) of the material used in the circuitry, also affects the obtainable signal speeds within a circuit. Impedance is principally the combination of resistance, capacitance and inductance which create electric and magnetic fields in a circuit. The impedance of a circuit is also called the characteristic impedance, as it depends solely on the characteristics of the materials used and their spatial relationship. Factors such as the dielectric constants of circuit materials and the widths of conductive signal traces primarily affect the characteristic impedance of an electronic circuit.
Matching the impedances of interconnecting circuitry with that of other electronic devices and connectors is often done in an attempt to ensure signal integrity in a circuit. This is because, particularly at high frequencies, signals may be reflected when impedance mismatches are present in a circuit. Such mismatches distort signals, increase rise times, and otherwise generate errors in data transmission. Consequently, impedance matching is often necessary to provide maximum power transfer between the connected electronic components and systems and to prevent signal reflections from forming along the signal paths.
As noted above, impedance in a printed circuit is directly related to the separation between signal traces separated by an insulating layer, as well as to the dielectric constant of the material in the insulating layer. The impedance of a given printed circuit board trace where the width is greater than the height of the trace are described by the following equations:
Zo
=120&pgr;/[(
W
eff
/h
)+1.393+0.667*ln[(
W
eff
/h
)+1.44]]*(&egr;
eff
)
1/2
&egr;
eff
=[(&egr;
r
+1)/2]+[(&egr;
r
−1)/2]*[1+((12*
h
)/
w
)]
−1/2
−[[(&egr;
r
−1)*(
t/h
)]/[4.6*(
w/h
)
1/2
]]; and
W
eff
=w+[
1.25*
t/&pgr;]*[
1+ln[2*
h/t
]]; where:
Zo=Characteristic impedance;
&egr;
eff
=Effective permittivity of a microstrip trace;
W
eff
=Effective width of a microstrip trace;
&egr;
r
=Relative permittivity of material between trace and ground plane;
h=Trace height over ground;
w=Trace width; and
t=Trace thickness.
Propagation delay, which is also related to the characteristics of the printed circuit board components, is described by the following equation:
Vp=
84.72*10
−12
*(&egr;
eff
)
1/2
; where
Vp=Propagation delay; and
&egr;
eff
=Effective permittivity of a microstrip trace.
One approach to the problem of managing propagation delay is to form expensive six or eight layer printed circuit boards which internally cancel propagation delay. However, there have also been numerous other approaches to controlling propagation delay, some of which include controlling or matching impedance in more simple four layer printed circuit boards.
U.S. Pat. No. 5,892,384 to Yamada et al. (Apr. 6, 1999) discloses a timing signal generation delay circuit to delay and transmit the clock signal after it detects propagation delay differences, also called skew, from a phase shift between two compared signals. By realigning the phases of the two signals by delaying one, the skew between the signals can be adjusted.
U.S. Pat. No. 5,926,397 to Yamanouchi (Jul. 20, 1999) discloses a series of individually tailored delay adjusting elements or cells to be inserted in relay spots within a system after considering the resistance, capacitance and inductance effects of the wires on the propagation delay.
U.S. Pat. No. 5,839,188 to Pommer (Nov. 24, 1998) discloses a specialized adhesive material to control the separation between printed circuit boards in multilayer circuit board applications to control propagation delay.
U.S. Pat. No. 5,929,199 to Snow et al. (Jul. 27, 1999) discloses a specific process for lowering the dielectric constant of a polymer and using that polymer in a printed circuit to reduce propagation delay.
U.S. Pat. No. 5,785,789 to Gagnon et al. (Jul. 28, 1998) discloses multilayer printed circuit board structures having partially cured, microsphere-filled resin layers which lower the dielectric constant of the overall structure to reduce propagation delay.
U.S. Pat. No. 5,945,886 to Millar (Aug. 31, 1999) discloses a method of reducing propagation delay by matching the impedance between two lines by matching the electrical lengths of the traces on a circuit board.
Although the prior art approaches to the problem of reducing propagation delay will each likely have an effect on propagation delay, each of these approaches also requires additional or specially tailored parts and layers, or processes which significantly add to the cost of fabricating the printed circuit board. Furthermore, the prior art methods do not consider varied characteristics within a circuit board, or differences between circuit boards, for a signal that crosses multiple circuit boards such as in the circuit configuration employed with a Rambus® dynamic random access memory (“RDRAM”).
SUMMARY OF THE INVENTION
The present invention addresses the problem of signal skew caused by variations in the propagation delay of corresponding signals in an electronic system. In a first embodiment of the invention, a plurality of printed circuit boards (“PCBs”) for use in memory modules are defined upon a common PCB array. The PCBs are laid out such that both a plurality of the sides of the PCBs which will be used for both the first sides of memory modules and a plurality of the sides of other PCBs which will be used for the second sides of memory modules are on the common first side of the array. The corresponding second side of the PCB array also includes PCBs respectively corresponding to the PCBs on the first side. The PCB arrays are then cut into individual PCBs or memory modules. Two PCBs or memory modules are matched and placed in a system
Siek Vuthe
TraskBritt
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