Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-11-04
2004-11-23
Brewster, William M. (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S303000, C257S306000
Reexamination Certificate
active
06822280
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior art Japanese Patent Application No. 2001-340198 filed on Nov. 6, 2001, the entire contents of which are incorporated by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory and a method of producing the same. Particularly, this invention relates to a cylinder-type stacked capacitor electrode for semiconductor memories and a method of producing such a type of stacked capacitor electrode.
One type of semiconductor memory is DRAM on/from which data can be written/retrieved. DRAM memory cells each consisting of one switching transistor and one capacitor have been widely used for semiconductor-memory integration owing to the simple structure.
One type of capacitor for such memory cells is a three-dimensionally structured capacitor that has been developed and used for maintaining capacitance at a certain degree or more in a reduced area on highly integrated DRAM.
The three-dimensionally structured capacitor is classified into a stacked type and a trench type. Especially, the stacked type is a good choice for highly integrated DRAM because of its stable performance with a relatively small capacitance and withstandingness against alpha ray and noises from circuitry.
Described with reference to
FIGS. 56
to
58
is a known memory cell having such a stacked-type capacitor (called a stacked capacitor hereinafter) with a cylinder-type lower electrode, that has been under study and improvements.
FIGS. 56
to
58
illustrate the known memory-cell structure:
FIG. 56
is a plan view;
FIG. 57
is a sectional view taken on line A-A′ of
FIG. 56
; and
FIG. 58
is a sectional view taken on line B-B′ of FIG.
56
.
Provided on a semiconductor substrate
501
in
FIGS. 56
to
58
are device-isolation regions
502
selectively formed thereon and MOS transistors (called just transistors herein after) Tr
1
, Tr
2
, . . . , each having source/drain diffusion layers
504
a
and
504
b
apart from each other and a gate electrode
507
coated with a silicon nitride film
506
provided via a gate insulating film
505
between the diffusion layers
504
a
and
504
b
, arranged, for example, in a matrix on a device-forming region
503
surrounded by the isolation regions
502
.
The gate electrodes
507
lie in a row direction (transversal direction in
FIG. 56
) each shared by the transistors adjacent to each other in the row direction, functioning as word lines W
0
, W
1
, . . . .
Also formed over the semiconductor substrate
501
is a first interlayer insulating film (silicon oxide film)
520
having a buried capacitor plug
510
and a buried bit-line plug
511
, both made of polycrystal silicon, on the diffusion layers
504
a
and
504
b
, respectively.
Formed on each first interlayer insulating film
520
having the capacitor plug
510
and the bit-line plug
511
is a second interlayer insulating film (silicon oxide film)
530
having a buried bit-line contact plug
512
made of, for example, tungsten coupled to the bit-line plug
511
.
Formed between the adjacent transistors are bit lines BL
0
, BL
1
, . . . , made of, for example, tungsten in a column direction (longitudinal direction in FIG.
56
), each bit line being electrically connected to the bit-line plug
511
via the bit-line contact plug
512
. Further formed on each second interlayer insulating film
530
is a third interlayer insulating film (silicon oxide film)
540
having the bit lines BL
0
, BL
1
, . . . , buried therein.
Formed between the two adjacent bit lines is a capacitor contact plug
513
reaching the capacitor plug
510
through the third and second interlayer insulating films
540
and
530
. The capacitor contact plug
513
and the capacitor plug
510
constitute a capacitor conductive plug
515
.
Formed on each third interlayer insulating film
540
having the capacitor contact plug
513
is an insulator mount
550
made of, for example, a silicon nitride film, as a capacitor mount.
Provided in each insulator mount
550
is a through hole
551
reaching the capacitor conductive plug
515
. Also formed is a cylinder-type lower electrode
561
having a rectangular bottom buried in each through hole
551
and penetrating into each insulator mount
550
, electrically connected to the diffusion layer
504
a
via the capacitor conductive plug
515
.
Each lower electrode
561
has dielectric films
562
formed on the inside and outside walls thereof. Formed on each lower electrode
561
via the dielectric film
562
is an upper electrode
563
. The lower electrode
561
, the dielectric film
562
and the upper electrode
563
constitute a capacitor
560
.
Each capacitor
560
has insulating films
570
formed on the inside and outside wall thereof. Although not shown, another upper electrode and wirings are provided on each capacitor
560
to constitute a memory cell having the transistor and the cylinder-type capacitor.
Described next with reference to
FIGS. 59A
to
66
B is a method of producing the known memory cell.
FIGS. 59A
to
66
B illustrate a sectional view for each production step, taken on line A-A′, line B-B′ or C-C′ of FIG.
56
.
As shown in
FIG. 59A
, the device-isolation regions
502
are selectively formed on the p-type semiconductor substrate
501
, followed by formation of the gate electrodes
507
on the device-forming region
503
surrounded by the device-isolation regions
502
, via the gate insulating films
505
. Each gate electrode is coated with the silicon nitride film
506
and has a laminated structure of a polycrystal silicon layer and a tungsten layer. The semiconductor substrate
501
is then doped with n-type impurities using the gate electrodes
507
as a mask, thus the n-type source/drain diffusion layers
504
a
and
504
b
being formed for the MOS transistors (FIG.
59
A).
A silicon oxide film is then deposited over the semiconductor substrate
501
having the gate electrodes
507
by plasma CVD (Chemical Vapor Deposition). The deposition is followed by CMP (Chemical Mechanical Polishing) for polishing the silicon oxide film until the silicon nitride film
506
on the gate electrodes
507
is exposed, having the first interlayer insulating film
520
buried between the two adjacent gate electrodes
507
, as shown in FIG.
59
B.
The first interlayer insulating film
520
formed on the diffusion layers
504
a
and
504
b
is selectively removed to provide openings
520
a
and
520
b
, respectively. Especially, the openings
520
b
are provided as having the width reaching over the device-isolation region
502
from the diffusion layer
504
b
. A phosphor-doped polycrystal silicon film is deposited over the semiconductor substrate
501
by LP (Low-Pressure)-CVD, followed by CMP, having the capacitor plugs
510
and the bit-line plugs
511
, both made of a low-resistance polycrystal silicon film, buried in the openings
520
a
and
520
b
, respectively, on the diffusion layers
504
a
and
504
b
, respectively (FIGS.
59
C and
59
D).
The second interlayer insulating film
530
made of, for example, silicon oxide is formed on the first interlayer insulating film
520
having the buried capacitor plugs
510
and the buried bit-line plugs
511
. The second interlayer insulating film
530
is then provided with openings
530
a
through each of which the bit-line plug
511
is exposed. A barrier metal film
531
is formed on the inside wall of each opening
530
a.
A conductive film made of, for example, tungsten is deposited on the second interlayer insulating film
530
, thus the opening
530
a
being filled with the conductive film. The bit-line contact
512
made of tungsten is then buried into the opening
530
a
after having the conductive film polished by CMP (FIGS.
60
A and
60
B).
Another tungsten film is deposited and patterned using a specific-patterned silicon nitride film
541
provided on the tungsten film as a mask, thus forming the bit lines BL each connected to the bit-line plug
511
v
Ito Eiji
Ito Hitoshi
Brewster William M.
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
LandOfFree
Semiconductor memory including forming beams connecting the... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory including forming beams connecting the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory including forming beams connecting the... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3298555