Logic circuit including combined pass transistor and CMOS...

Details Logic circuit including combined pass transistor and CMOS... Logic circuit including combined pass transistor and CMOS...

2002-06-25

2004-11-16

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C326S112000, C326S113000, C326S114000

Reexamination Certificate

active

06820242

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a small-area, high-speed, low power consumption logic circuit which includes combined pass transistor and CMOS circuits, and also to a method of synthesizing from a Boolean function a small-area, high-speed, low power consumption logic circuit which includes combined pass transistor and CMOS circuits.
BACKGROUND ART
In a pass transistor logic circuit as one of logic circuits, a single transistor may have various logical functions. Thus, many researches are published which aim to fabricate pass transistor logic circuits well and replace all the conventional CMOS logic circuits with the pass logic circuits to obtain an LSI, while greatly reducing the number of transistors of the LSI to reduce its area and power consumption.
One of the researches discloses a method of synthesizing a pass transistor logic circuit having an intended logical faculty by replacing a respective one of nodes of a binary decision diagram produced from a Boolean function with a 2-input, 1-output, 1-control input pass transistor selector.
The binary decision diagram is a graphic representation of a Boolean function with a binary tree of nodes having two branches called branches “1” and “0”. It is capable of expressing a complicated Boolean function concisely. Thus, this is watched as a method of synthesizing a compact pass transistor logic circuit which has an intended logical function with fewer transistors than the conventional transistor logic circuit.
For example, Proceeding of IEEE 1994 Custom Integrated Circuits Conference, pp. 603-606 (hereinafter referred to as “document 1”) proposes a method of synthesizing a desired pass transistor logic circuit by fabricating a 2-input, 1-output pass transistor selector with n-channel field effect transistors alone, and inserting buffer inverters to reduce a delay time as requested.
The conventional CMOS logic circuit requires as many low-performance p-channel field effect transistors as n-channel field effect transistors. However, the great part of the pass transistor logic circuit synthesized by the method described in the document 1 can be composed of higher-performance n-channel field effect transistors alone excluding buffer inverters. Thus, a high-performance circuit is obtained which is reduced in area, delay time and power consumption compared to the conventional CMOS logic circuit.
IEEE Symposium on Low Power Electronics, 1995, pp.14-15 (hereinafter referred to as “document 2”) proposes a method which includes further development of the method of document 1. The method of document 2 is characterized in that a pass transistor logic circuit is synthesized on the basis of multi-level binary decision diagram, which is produced in the following process:
(1-1) A binary decision diagram is created from a Boolean function; and
(1-2) Partial trees which have different nodes indicated by a branch “0” or “1”, but which are exactly the same in graphic shape (the same-type partial trees) are extracted, and nodes controlled by the same-type partial tree are newly produced.
By beneficial effects of (1-2), a Boolean function is expressed with fewer nodes than a regular binary decision diagram in the multi-stage binary decision diagram. Thus, a pass transistor logic circuit having an intended logical function can be synthesized with fewer transistors than those described in document 1. Since the number of nodes connected in series is suppressed so that the number of stages of the synthesized pass transistor circuits is suppressed as well. Thus, a pass transistor logic circuit reduced in delay time, area and power consumption compared to that of document 1 can be synthesized.
Japanese Institute of Electronics, Information and Communication Engineers, technical report VLD 95-115, Vol. 95, No. 119, pp. 1-6 (hereinafter referred to as “document 3”) proposes a method of synthesizing a pass transistor logic circuit reduced in power consumption. In this method, like document 2, a pass transistor logic circuit is synthesized based on the multi-stage binary decision diagram. By using a minimum number of delay time improving buffer inverters, a pass transistor logic circuit of further reduced power consumption is synthesized.
JP-A-1-129611, JP-A-1-216622, JP-A-1-256219 and JP-A-7-130856 describe pass transistor circuits.
Furthermore, JP-A-7-168874 and JP-A-9-6821 describe a method of synthesizing a pass transistor logic circuit.
DISCLOSURE OF THE INVENTION
The inventors actually created binary decision graphs based on several Boolean functions and synthesized pass transistor logic circuits using the methods described in the documents 1, 2 and 3. As a result, for a certain Boolean function, a pass transistor logic circuit was successfully synthesized which was reduced greatly in the number of transistors, area, delay time and power consumption compared to the conventional CMOS logic circuits. However, for another Boolean function, we found that a pass logic circuit obtained conversely increased in area, delay time, and power consumption.
For example, when a simple 2-input NAND logic is synthesized with a pass transistor logic circuit, using each of the methods of the documents 1, 2 and 3, the logic circuit obtained is composed of six transistors shown by Cl in FIG.
4
A. However, when it is synthesized with a CMOS logic circuit, the logic circuit obtained is a simplified circuit (C
2
of
FIG. 4A
) composed of four transistors. When a 2-input NOR logic is synthesized with a pass transistor logic circuit, the resulting circuit contains six transistors (C
3
of FIG.
4
A), while when it is synthesized with a CMOS logic circuit, the resulting circuit contains four transistors (C
4
of FIG.
4
A).
As shown in
FIGS. 4A-4C
, for NAND logic and NOR logic, a circuit composed of CMOS gates has better performance with reference to area and delay time excluding power consumption than that composed of a pass transistor logic circuit As just described above, the pass transistor selector circuit is not suitable for the NAND or NOR logic, but suitable for a selector logic which selects one of signals using another signal because of its circuit composition. The NAND/NOR logic is a basic circuit of the CMOS circuit, so that it is natural that the CMOS circuit can fabricate a higher-performance logic circuit than the pass transistor circuit. However, even in NAND and NOR logics, the pass transistor circuit is lower in power consumption than the CMOS circuit.
This point is overlooked in the researches of the conventional pass transistor circuits, which indicates that the pass transistor circuit and CMOS circuits have their strongest and weakest points and that the pass transistor circuits are not always superior to the CMOS circuits in every respect. Which of the pass transistor circuits and the CMOS circuits is superior to the other varies depending on a preferentially handled one of area, delay time and power consumption as the circuit characteristic of a logic circuit to be synthesized.
Unlike the age in which the logic circuits were designed by peopleos hands, logic circuits are designed, using a high-class language such as HDL (Hardware Description Language) at present. Thus, it is very important how a logic composed of combined If-Then-Else (corresponding to a selector logic) and Boolean algebra is realized, using a compact logic circuit.
As described above, for any logic, or when any one of area, delay time and power consumption as the circuit characteristics takes preference over the others characteristics, a logic circuit having excellent circuit characteristics cannot be composed only of pass transistor circuits. Thus, a pass transistor/CMOS collaborated logic circuit is required to be produced which includes a well combination of advantages of pass transistor circuits and CMOS circuits so that the pass transistor circuits and CMOS circuits cooperate well with each other. In order to produce an excellent-performance LSI chip reduced in area, delay time, and power consumption, it has a very important significance to provide a method of auto

Affiliated with

Also associated with

Rating

Logic circuit including combined pass transistor and CMOS... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Logic circuit including combined pass transistor and CMOS..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic circuit including combined pass transistor and CMOS... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3297243