Semiconductor memory device having redundancy system

Details Semiconductor memory device having redundancy system Semiconductor memory device having redundancy system

2003-04-23

2004-12-21

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700

Reexamination Certificate

active

06834016

ABSTRACT:

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-005562, filed Jan. 12, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a redundancy system.
2. Description of the Related Art
FIG. 15
is a block diagram schematically showing the arrangement of a redundancy system in a conventional semiconductor memory device. In
FIG. 15
, a fuse set
100
surrounded by a broken line is composed of a plurality of address fuses FUSE
0
to FUSEn, which are disposed in correspondence to n+1 input address signals A
0
to An supplied via address lines for programming a defective addresses of a memory array in the semiconductor memory device, and a master fuse FUSEM which is provided to prevent the redundant elements from being selected when they are not used.
The outputs from the plurality of address fuses FUSE
0
to FUSEn and the output from the master fuse FUSEM are latched by a plurality of fuse latch circuits FLATCH
0
TO FLATECHn and a fuse latch circuit FLATCHM disposed in correspondence to them, and then the outputs from the fuse latch circuits are supplied to corresponding address comparators ACOMP
0
to ACOMPn each composed of an EX-NOR circuit together with the input address signals A
0
to An.
Whether the latch outputs FOUT
0
to FOUTn from the fuse latch circuits FLATCH
0
to FLATCHn are set to “H” or “L” is determined according to the states of the address fuses FUSE
0
to FUSEn, that is, based on whether or not the fuses are blown.
Then, as to each of the input address signals A
0
to An, it is determined by any one of the address comparators whether the H- or L-level of a corresponding one of the input address signals agrees with the H- or L-level of a corresponding one of the latch outputs FOUT
0
to FOUTn. Subsequently, when all the input address signals A
0
to An agree with programmed addresses, that is, agree with the latch outputs FOUT
0
to FOUTn as well as when the master fuse FUSEM is blown and a latch output FOUTM goes to “H”, a NAND circuit HD acting as a hit detector outputs an L-signal bHIT indicating a redundancy mode.
Incidentally, the redundancy system disposed in the semiconductor memory device has a lot of fuses. Thus, it is very important to dispose an overall redundancy circuit including the fuses themselves as compact as possible in layout to reduce the size of the semiconductor memory device.
FIGS. 16A and 16B
are views schematically showing a layout of a plurality of fuses. Fuses for redundancy are usually arranged along an address bus. However, it is impossible to arrange a lot of fuses in one stage of a fuse row that is, in one stage of a fuse bank
110
in unlimited quantities, and there is a case in which they must be accommodated within a width W of FIG.
16
A. The width of the fuse bank
110
is restricted by layouts other than the layout of the redundancy system, and the like. However, if even only one necessary fuse (for example, fuse FUSEk+1) cannot be accommodated in the width W, the one stage of the fuse row
110
must be increased to two stages of fuse banks
112
and
113
as shown in FIG.
16
B. An increase in the number of the stages to the two stages increases the area of the redundancy layout because the height of a redundancy layout is increased from H
1
to H
2
. As a result, a chip area is also increased. That is, there is a case in which a slight difference of the number of fuses greatly changes the layout area of a redundancy circuit.
BRIEF SUMMARY OF THE INVENTION
A semiconductor memory device according to one aspect of the present invention having a memory system and a redundancy system including redundant elements for repairing a plurality of defects in the memory system, comprising: a plurality of address fuse sets each including address fuses for programming a defective address in the memory system; and a master fuse for preventing a corresponding redundant element from being selected when the redundant element is not used, wherein at least one master fuse is shared by at least two fuse sets among the plurality of address fuse sets.


REFERENCES:
patent: 5940335 (1999-08-01), Kirihata
patent: 5991211 (1999-11-01), Kato et al.
patent: 5999463 (1999-12-01), Park et al.
patent: 6243305 (2001-06-01), Brady
patent: 6388941 (2002-05-01), Otori et al.
patent: 6400620 (2002-06-01), Yoo
patent: 6430101 (2002-08-01), Toda
patent: 6480428 (2002-11-01), Zheng et al.
patent: 05-166394 (1993-07-01), None
patent: 1999-014031 (1999-02-01), None

Affiliated with

Also associated with

Rating

Semiconductor memory device having redundancy system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having redundancy system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having redundancy system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3297195