System and method for quick self-refresh exit with...

Details System and method for quick self-refresh exit with... System and method for quick self-refresh exit with...

2002-04-23

2004-02-17

Lam, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233100, C365S236000

Reexamination Certificate

active

06693837

ABSTRACT:

TECHNICAL FIELD
The present invention is directed to dynamic random access memory (“DRAM”) devices. More particularly, the present invention is directed to a system and method allowing DRAM devices to more efficiently exit from a self-refresh state so that the DRAM device can resume processing valid commands more quickly.
BACKGROUND OF THE INVENTION
Most computers and other digital systems have a system memory which often consists of dynamic random access memory (“DRAM”) devices. DRAM devices are fairly inexpensive because a DRAM memory cell needs relatively few components to store a data bit as compared with other types of memory cells. Generally a DRAM memory cell consists of a transistor/capacitor pair whereas, in a static random access device (SRAM), each memory cell comprises four or more transistors. Thus, DRAM memory cells have fewer components than SRAM memory cells. As a result, DRAM arrays occupy far less area on a semiconductor substrate compared to SRAM arrays of the same size. Thus, DRAM devices are far less expensive to produce than SRAM devices. A large system memory can be implemented using DRAM devices for relatively low cost, making DRAM devices a very popular choice in many devices requiring a large memory capacity.
On the other hand, while DRAM devices are less expensive to produce than SRAM devices, DRAM devices suffer from the disadvantage that their memory cells must be continually refreshed because of the inherently transitory nature of their storage technology. Over time, the voltage stored across the capacitor dissipates as a result of current leakage. To offset this problem, each memory cell regularly must be refreshed within a maximum refresh interval by determining whether a high or low voltage was stored across that capacitor, and recharging the capacitor to that voltage. The refresh process, which basically involves reading a memory cell through a sense amplifier to recharge the memory cell's capacitor, is well known in the art, and it is reasonably simple and quick.
Notwithstanding how quick the refresh process might be, however, having to continually refresh all the memory cells in a DRAM memory array impedes the intended function of the memory: reading and writing data in response to processor directives. Even though memory cells are refreshed an entire row at a time, memory banks may be thousands of rows deep, and each row must be refreshed many times per second. Collectively, thousands upon thousands of refresh operations are required every second to preserve the contents of the memory cells in a DRAM device—thousands of operations during which the DRAM device is precluded from performing desired read and write functions. Moreover, unless the memory array is equipped with a dual accessing mechanism, a row cache device, or a functionally similar means, the array can be neither read from nor written to during a refresh cycle without interrupting or destroying the cycle. If the central processing unit or other controller initiates a memory read or write operation during a refresh cycle, the processor or controller needs to wait for completion of that refresh cycle along with any corresponding wait states or delay intervals. Clearly, waiting for refresh procedures slows the operational throughput of the computing system.
FIG. 1
depicts a conventional DRAM device
100
. The DRAM device
100
is accessed through the address lines
110
, the data lines
112
, and a number of control lines
120
-
132
. These control lines include CKE (clock enable)
120
, CK* (clock signal—low)
122
, CK (clock signal)
124
, CS* (chip select—low enable)
126
, WE* (write select—low enable)
128
, CAS* (column address strobe—low enable)
130
, and RAS* (row address strobe—low enable). The address lines
110
, data lines
112
, and control lines
120
-
132
, enable the system to read and write data to the actual memory banks
150
, as well as control the refreshing of the DRAM device
100
.
The control logic
160
controls the read, write, and refresh operations of the DRAM device
100
. The control logic
160
directs the operations of the DRAM device
100
as a function of the signals received at the control lines
120
-
132
. Numerous other elements of the DRAM device
100
are depicted in
FIG. 1
, but the refresh counter
170
and the self-refresh control logic
180
are particularly relevant to this discussion.
The refresh counter
170
is an integral component in refreshing the DRAM device
100
. The refresh counter
170
maintains a count corresponding to the row number in the memory banks
150
that was last refreshed or, if a row refresh is in progress, the number of the row currently being refreshed. Once a command is received to refresh a row, the refresh counter
170
is incremented by one, and the row of the memory banks
150
corresponding to the updated count stored in the refresh counter
170
is refreshed. The refresh counter
170
thereby tracks what row is next to be refreshed, controlling the sequencing of row refreshes.
Tracking the count maintained by the refresh counter
170
, the rows of the memory banks
150
can be refreshed in either burst refresh or distributed refresh. Using burst refresh, all the rows of the memory banks
150
are refreshed in immediate succession, one after the other, for as long as it takes to refresh every row of the device. Operationally, the refresh counter
170
is incremented, the row indicated by the refresh counter
170
is refreshed, and this process repeats until each row of the memory banks
150
has been refreshed. Once all the rows have been successively refreshed, the DRAM device
100
once more is available for read and write operations until the memory banks
150
of the DRAM device
100
must again all be refreshed.
In a distributed refresh, one row of the memory banks
150
is refreshed at a time, then the DRAM device
100
is made available for useful operations until the next individual row of the memory banks
150
needs to be refreshed. As the designation “distributed” implies, this type of refresh distributes the time required to refresh every row in the memory banks
150
over the entire maximum refresh interval, instead of ceasing all read and write operations for the relatively long interval required to refresh every row in the memory banks
150
as in a burst refresh. Specifically, for each refresh command received, the refresh counter
170
is incremented, the row corresponding to the number indicated by the refresh counter
170
is refreshed, then the DRAM device
100
is made available for read and write operations until the next refresh command is received. This process repeats continuously. In a typical DRAM, having 4,096 rows and a maximum refresh interval of 64 milliseconds in its operational mode, a command to refresh one row would have to be issued approximately every 15 to 16 microseconds.
In addition, in a typical DRAM device, there are also two different types of refresh modes: auto-refresh and self-refresh. The first type, auto-refresh, is the command given to initiate a single refresh command. Whether the system employs burst refresh or distributed refresh to refresh its memory devices, issuance of an auto-refresh command initiates one refresh cycle for the entire memory bank or for a single row, respectively. Auto-refresh is, therefore, the “standard” refresh command used to refresh memory devices during normal operation. An auto-refresh command is issued to the DRAM device
100
by driving the CKE
120
and WE*
128
control lines high, and driving the CS*
126
, RAS*
130
and CAS*
132
control lines low.
Auto-refresh operates synchronously with the system clock. With the CKE
120
and WE*
128
control lines driven high, and the CS*
126
, RAS*
130
and CAS*
132
control lines driven low, the rising edge of the next clock signal initiates an auto-refresh of the next row of the memory banks
150
. As is known in the art, the rising edge of the next clock signal is that point where the clock signals received at the CK*
122
and CK
124
control lines cross. As previ

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