Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-10-16
2004-02-10
Baderman, Scott (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S034000, C714S035000, C717S129000
Reexamination Certificate
active
06691246
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a system and method of processing partially defective memories. More particularly, it relates to a system and method of adjusting a program code that either has not yet been loaded into or already resides in memory. The present invention allows program codes to be loaded into a memory with partially defective memory cells and further be executed.
DESCRIPTION OF THE PRIOR ART
In the past, memory integrated circuits (ICs) containing any defective memory cell generally will not be sold on the market. To reduce the number of the memory ICs that are thrown away due to one or more defects, there are at present many techniques that can repair defective memory ICs thereby allowing them to work normally.
For example, U.S. Pat. No. 4,939,694 disclosed a memory system that has self-testing and self-repairing functions. The memory system can perform an on-site self-test process to locate defective memory cells. Once these defective memory cells are located, the memory system will use an error correction code engine to correct these defective memory cells. When the error correction code engine becomes overburdened with defective memory cells, the memory system automatically deletes these defective memory cells.
Furthermore, U.S. Pat. No. 5,644,541 disclosed a technique of using substitution memories to correct semiconductor memories with defective memory cells. All access routes to these bad bit-locations are redirected to good memory cells within the substitution memory by using a mapping logic circuit, whereby the defective memory cells are replaced.
A fault-tolerating memory system, disclosed in U.S. Pat. No. 5,278,847, uses an error detecting and correcting code (EDAC). Reliability of storage data can be determined by using the EDAC for each data cell and for adding spare-bits.
In U.S. Pat. No. 5,579,266, a laser-repairing technique and a programmable fuse repairing technique are used to deal with defective memory cells, wherein redundant memories can be used to replace defective memories.
In fact, the error-detecting and repairing technique disclosed in U.S. Pat. No. 4,939,694, the encoding and spare bit technique disclosed in U.S. Pat. No. 5,278,847, and the access-redirecting technique disclosed in U.S. Pat. No. 5,644,541 do not only complicate the hardware design, but also suffer an execution overhead as programs are executed. Further, for the redundancy memory technique disclosed in U.S. Pat. No. 5,579,266, the hardware design and the practical procedure for repairing defective memory cells are also complicated.
On the other hand, an executable machine code program is generated from the source code of a computer program by using compilers and linkers. The machine code program can be directly downloaded to memories for execution.
FIG. 1
(PRIOR ART) shows a system structure of a general single chip computer or a system-on-a-chip. As shown in
FIG. 1
, the system comprises a central processing unit (CPU) or microprocessor
1
, random access memories (RAMs)
3
, read-only memory (ROMs)
5
, an I/O interface circuit
7
, and external storage devices
9
such as hard-disk drives, floppy disk drives, or CD-ROM drives. The general operation is that the CPU
1
loads an executable machine code program from the I/O interface circuit
7
or the external storage devices
9
into the RAMs
3
via data/address bus
10
. Generally, a machine code program is comprised of three segment types, instruction segments, data segments, and stack segments, respectively. The CPU
1
executes the machine code program from the entry point of one of the instruction segments.
FIG. 2
(PRIOR ART) is a flow chart illustrating the process of executing a machine code program. First, an entry point is acquired (S
1
). Then, the address of the next instruction is fetched (S
2
). According to the address, the opcode of the next instruction can be fetched (S
3
). Then, the opcode is decoded (S
4
). Next, determination of whether one or more operands are needed for the current instruction can be determined by the decoded information of the current instruction. Then, the operand can be read from the follow-up address, if any (S
5
). Finally, the instruction is executed by the operation defined in the fetched opcode and the data/reference addresses defined in the operand (S
6
) . If the current instruction is a termination instruction (S
7
), the process of executing the machine code program finishes (S
8
). Otherwise, the process goes back to step S
2
to acquire the address of the next instruction. Apparently, it is possible that each instruction does not have the same number of bytes. The instruction length depends on the type of the CPU. Generally, there are two types of instruction sets applied in various CPUs, the variable-length instruction set and the constant length instruction set.
The above-described execution procedure only can be applied to the instruction segments of the machine code program. If the same execution procedure is applied to other segments, such as the data segments or the stack segments, the decoding result will be erroneous. In this case, when a data byte is decoded into a faulty opcode by the CPU
1
, several sequent data will be mistaken for operands according to the faulty opcode. Generally, the CPU
1
cannot automatically distinguish the instruction segment from the data segment or the stack segment via standard fetching and decoding actions. Furthermore, the instruction segments and the data/stack segments of the program cannot be randomly is broken. The instruction pools must be broken based on each complete instruction, including its opcode and the follow-up operands. Generally, the data/stack segments cannot be broken because some of the interrelation within the data/stack segments only can be determined during execution, such as array data structures.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a system and method of processing a partially defective memory. The storage pattern of a program code, which has not been loaded yet or has existed in the partially defective memories, can be modified to avoid the use of the defective memory cells without changing the hardware design or increasing the execution overhead.
Accordingly, the invention provides a method of processing a partially defective memory for loading a machine code program into a memory device with a plurality of memory cells. For example, suppose that the memory device has at least one defective memory cell. The original machine code program is scanned first to determine a first break point and a second break point at the locations before and after the defective address corresponding to the defective memory cell in the original machine code program. Then the code block between the first break point and the second break point is moved to an address space between a first address and a second address that does not include the defective address. When the moved code block includes at least one executable instruction (i.e. includes the instruction segment), it is necessary to link the moved block code and the unmoved portion of the original machine code program in execution sequence. If there are addressing references between the moved code block and the unmoved portion of the original machine code program or within the moved code block code, these addressing references should be adjusted. At last, the unmoved portion of the original machine code program, the linking instructions and the moved code block are sequentially loaded to the memory. Since the program is loaded by using the aforementioned method, it is in an executable status and will not be attached by the defective memory cells. In other words, the memory device can still work normally even if there are defective memory cells in the memory device. Further, the above processing procedure does not need to alter or modify the hardware circuitry. Therefore, the cost is quite low.
Further, if the source codes of the machine code program have been modularized, it is convenient to deter
Baderman Scott
Ladas & Parry
Winbond Electronics Corp.
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