Semiconductor memory device having full depletion type logic...

Details Semiconductor memory device having full depletion type logic... Semiconductor memory device having full depletion type logic...

2002-01-31

2004-10-26

Lee, Eddie (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S350000, C257S392000

Reexamination Certificate

active

06809381

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device and a method of fabricating the same.
This application is a counterpart application of Japanese application Serial Number 313593/2001, filed Oct. 11, 2001, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
There has been growing attention to be paid to Silicon On Insulator (hereinafter referred to as an SOI) during the development of a tomorrow's LSIs which can operate at a low voltage with low power consumption. The SOI technique is a technique for forming elements such as transistors on a silicon layer formed on a insulating layer. A semiconductor device fabricated using this technique has an advantage in that it operates at a low voltage with low power consumption. For an application using the current SOL technique, CMOS and the like is mainstream, and hence the SOI technique is not frequently applied to memory products such as a DRAM. However, there is a demand for low voltage with low power consumption even for memories. It has been difficult to fabricate memories which operate at a low voltage with low power consumption compared with current memories using conventional bulk type transistors. Accordingly, the application of the SOI technique to memories has been studied.
A method of fabricating a full depletion type semiconductor device having a conventional SOI structure is described with reference to FIG.
4
(A) to FIG.
4
(E).
Firstly, an embedded oxide film layer
20
having a thickness on the order of 1000 to 2000 Å is formed on a silicon substrate
10
, and a silicon layer
30
having a thickness on the order of 500 to 1000 Å is formed on the embedded oxide film layer
20
, as shown in FIG.
4
(A).
Secondly, a pad oxide film
35
having a thickness on the order of 50 to 200 Å is formed on the silicon layer
30
, and nitride films
36
each having a thickness on the order of 500 to 3000 Å and having openings on a field oxide film formation region are formed on a remaining pad oxide film
35
using a normal photolithography/etching technique, as shown in FIG.
4
(B).
Thirdly, the silicon layer
30
is subjected to a thermal oxidation using the nitride films
36
serving as a mask so as to form field oxide films
40
each having a thickness (on the order of 1000 to 2000 Å) to reach the embedded oxide film layer
20
. Thereafter, the remaining nitride films
36
and the remaining pad oxide film
35
are respectively removed to form a shape, as shown in FIG.
4
(C).
Fourthly, the silicon layer
30
which are separated in elements (hereinafter referred to as elementally separated) is doped with an impurity so as to render the silicon layer
30
formed on the transistor formation region conductive, as shown in FIG.
4
(D).
Lastly, a gate oxide film
50
is formed on the silicon layer
30
on the transistor formation region, then gate electrodes
60
are formed on the gate oxide film
50
using a normal photolithography technique and etching technique. Further, the silicon layer
30
is doped with an impurity using the gate electrodes
60
serving as a mask, thereby forming a source and drain regions
71
of the transistor. As a result, the semiconductor device using the SOI technique is accomplished, as shown in
FIG. 4
(E).
However, if the forgoing transistor is applied to a transfer gate of a memory cell, electric charges are prone to accumulate in a region under a gate electrode of the transistor (hereinafter referred to as a body region). As a result, there is a likelihood that a source and a drain of the transistor are electrically connected to each other by accumulated electric charges even if no voltage is applied to the gate electrode of the transistor. Under such circumstances, electric charges stored in a capacitor connected to the transistor leak, and hence data stored in the memory cell is destroyed.
Although a threshold value (hereinafter referred to as threshold voltage Vt) of a gate voltage of the SOI transistor is of the order of 1.0 to 1.2 volt, there is a possibility that the threshold voltage Vt becomes not more than 0.7 volt owing to electric charges accumulated in a body region of the transistor. Under such circumstances, the source and the drain are electrically connected to each other, as set forth above, and hence there occurs a phenomenon of a pass gate leakage (sub-threshold leakage) where electric charges accumulated in a capacitor leak, resulting in the occurrence of possibility that data stored in the memory cell is destroyed.
SUMMARY OF THE INVENTION
To solve the forgoing problems, a semiconductor device of the invention has a first silicon layer and a second silicon layer respectively formed on a silicon substrate by way of an insulating layer. Full depletion type transistors for use in a logical circuit are formed on the first silicon layer while partial depletion type transistors for use in a memory cell circuit are formed on the second silicon layer. Further, a potential of the second silicon layer is fixed at a fixed value.
Further, the semiconductor device is fabricated by forming the first and second silicon layers on the insulating layer, forming nitride film patterns on the first and second silicon layers, forming a first element separation film contacting the insulating layer for elementally separating the first silicon layer by subjecting the first and second silicon layers to oxidation using the nitride film patterns serving as a mask, forming a second element separation film on the insulating layer by way of the second silicon layer for elementally separating the second silicon layer, removing the nitride film patterns, forming full depletion type transistors on the first silicon layer and forming partial depletion type transistors on the second silicon layer.


REFERENCES:
patent: 5674760 (1997-10-01), Hong
patent: 6208010 (2001-03-01), Nakazato et al.
patent: 6215155 (2001-04-01), Wollesen
patent: 6407427 (2002-06-01), Oh
patent: 6632710 (2003-10-01), Takahashi
patent: 2002/0109187 (2002-08-01), Matsumoto et al.
patent: 05-291574 (1993-11-01), None
patent: 06-291265 (1994-10-01), None
patent: 09-260679 (1997-10-01), None
patent: 09260679 (1997-10-01), None
patent: 10-012717 (1998-01-01), None
patent: 11-298001 (1999-10-01), None
patent: 11298001 (1999-10-01), None
patent: 2001-44441 (2001-02-01), None
Yo-Hwan Koh et al., Body-Contacted SOI MOSFET Structure With Fully Bulk CMOS Compatible Layout And Process (3 Pages); IEEE Election Device Letters, vol. 18. No. 3, Mar. 1997.
Yo-Hwan Koh et al., 1 Giga Bit SOI DRAM With Fully Bulk Compatible Process and Body-Contacted SOI MOSFET Structure (4 Pages): IEDM Tech. Fig., 1997. pp. 24.1.1-24.1.4.

Affiliated with

Also associated with

Rating

Semiconductor memory device having full depletion type logic... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having full depletion type logic..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having full depletion type logic... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3295186