Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-30
2004-12-07
Munson, Gene M. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S506000
Reexamination Certificate
active
06828636
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device in general, and more particularly to a semiconductor device obtained with an improved method of manufacturing a semiconductor device capable of preventing excessive CMP (chemical mechanical polishing) of a resistive band region and margin deterioration in processing in a subsequent step.
2. Description of the Background Art
A resistive zone is used for altering a potential of a circuit. As each interconnection comes to have lower resistance due to reduced size and increased speed, many recent devices use source/drain (S/D) as a resistive zone.
FIGS. 15
to
17
are plan views showing steps in a method of forming a resistive zone according to a conventional technique.
FIGS. 18
to
25
are cross-sectional views showing a method of forming a resistive zone according to a conventional technique.
FIGS. 18
to
24
show cross-sections viewed along the line XVIII—XVIII in FIG.
15
.
FIG. 15
is a plan view showing active regions
2
,
3
(to be provided as resistive zones) formed according to a conventional technique.
FIG. 16
is a plan view showing a transfer gate (TG)
4
formed according to a conventional technique.
FIG. 17
shows contact holes (CH)
5
,
6
,
9
,
10
,
12
formed according to a conventional technique. In these figures, reference numeral
1
represents a resistive band region; reference numeral
7
represents an active region in a densely-patterned portion; reference numeral
8
represents a TG in the densely-patterned portion; reference numeral
11
represents the densely-patterned portion; and reference numeral
31
represents an isolation oxide film region.
Detailed description will now be given.
Referring to
FIG. 18
, according to conventional STI (Shallow Trench Isolation) technique, an oxide film
14
and a nitride film
15
are formed on the surface of a silicon substrate
13
, and active regions
2
,
3
are patterned.
Referring to
FIG. 19
, in order to remove etching-induced damage in silicon substrate
13
, the surface of a trench undergoes oxidization to form an oxide film
161
. The oxidization also serves to round an upper corner and a lower corner of the trench. The widths of active regions
2
,
3
, however, are made narrower than in patterning since a sidewall of the trench is oxidized.
Referring to
FIG. 20
, an oxide film
16
fills the inside of the trench. SiO
2
film formed with HDP (High Density Plasma) is used as burying oxide film
16
.
Thereafter, chemical mechanical polishing (CMP) is performed in order to remove oxide film
16
on nitride film
15
. CMP is performed to be stopped at nitride film
15
. It is difficult, however, to stop CMP at nitride film
15
because, in a resistive zone pattern as shown in
FIG. 15
, many regions are surrounded by an isolation oxide film
31
. As a result, resistive band region
1
will be overpolished. Such overpolishing is more likely where the ratio of the area (area occupancy ratio) of a resistive zone (an active region)
2
relative to resistive band region
1
is lowered. In particular, when the area occupancy ratio of the active region per 10 &mgr;m□ (herein representing 10 &mgr;m×10 &mgr;m; that is, a square having sides of 10 &mgr;m long) is 20% or lower, overpolishing will occur significantly.
When overpolishing occurs, patterns surrounding resistive band region
1
will be damaged due to the overpolishing, as shown in FIG.
21
. Related problems will be explained in the following.
In
FIG. 22
, nitride film
15
and oxide film
14
are removed after CMP. With the removal of nitride film
15
and oxide film
14
, the surface of burying oxide film
16
will cave in and an upper corner
18
of the trench in active region
3
in the vicinity of the resistive zone is also exposed.
In
FIG. 23
, a gate oxide film (not shown) and a TG
17
are further formed, and then patterned.
Referring to
FIG. 24
, source/drain injection
19
is performed to form source/drain regions (not shown) of a transistor and a conductive portion
20
of resistive zone
2
.
Referring to
FIGS. 23 and 24
, upper corner
18
of the trench will have top side and sidewall portions covered with TG
17
. Accordingly, electric field concentration is likely in these portions and reverse narrow channel effect will occur. Consequently, a threshold voltage (V
th
) of a transistor is made lower than a designed value.
A cross-sectional view along the line XXV—XXV in
FIG. 17
corresponds to that along the line XXV—XXV in FIG.
25
.
In
FIG. 25
, after forming source/drain regions, an interlayer oxide film
21
is formed and contact holes
22
,
23
are opened according to a conventional technique. Here, in resistive band region
1
, the height of burying oxide film
16
is lower than that of densely-patterned portion
11
which was not overpolished with CMP. In addition, as the area occupancy ratio of TG is low in resistive band region
1
, there will be a level difference
24
with respect to densely-patterned portion
11
where the area occupancy ratio of TG is high. Level difference
24
results from excessive CMP and difference in the area occupancy ratio of TG. Level difference
24
causes photomechanical process of contact holes
22
,
23
to be easily defocused. Deterioration of such photomechanical process margin will occur also in processing in a subsequent step. In addition, etching residue tends to be left in a subsequent etching step.
SUMMARY OF THE INVENTION
The present invention was made to solve the above-described problems. An object of the present invention is to provide an improved method of manufacturing a semiconductor device capable of preventing excessive CMP in a resistive region and forming a resistive zone with an active region.
Another object of the present invention is to provide an improved method of manufacturing a semiconductor device capable of preventing margin deterioration in processing and forming a resistive zone with an active region.
Another object of the present invention is to provide a semiconductor device obtained with such a method.
A semiconductor device according to a first aspect involves a semiconductor device using a source/drain impurity diffusion layer as a resistive zone. The device has a semiconductor substrate, on which a resistive band region to form the resistive zone, having at least a portion of the surface provided as an active region, is formed. The resistive zone is provided in the resistive band region. A word line is arranged on the semiconductor substrate so as to surround the resistive zone. In the resistive band region, the area occupancy ratio of the active region per 10 &mgr;m □ is set to be 40% or higher.
A second aspect involves a semiconductor device using a source/drain impurity diffusion layer as a resistive zone. The device has a semiconductor substrate, on which a resistive band region to form the resistive zone, having at least a portion of a surface as an active region, is formed. In the resistive band region, a resistive zone surrounded by an isolation region is provided. A dummy active region is arranged in the isolation region.
A third aspect involves a semiconductor device using a source/drain impurity diffusion layer as a resistive zone. The device has a semiconductor substrate, on which a resistive band region to form the resistive zone, having at least a portion of a surface as an active region, is formed. In the resistive band region, a resistive zone surrounded by an isolation region is provided. A dummy word line is arranged in the isolation region.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 6111304 (2000-08-01), Sonoda
patent: 6172389 (2001-01-01), Sakoh
patent: 8-139271 (1996-05-01), None
patent: 2000-196019 (2000-07-01), None
Fujiishi Yoshitaka
Kawasaki Satoshi
Munson Gene M.
Renesas Technology Corp.
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