Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-06-28
2004-02-24
Le, Vu A. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C702S089000
Reexamination Certificate
active
06697291
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for checking a conductive connection between contact points of semiconductor chips formed on a wafer and mating contacts of a test head.
Methods are already known by which the electrically conductive connection between the contact pins of a test head and the contact points of the semiconductor chips formed on a wafer can be checked. The test head usually extends over a group of 4 to 64 semiconductor chips. If 64 semiconductor chips are intended to be tested in parallel and each of the semiconductor chips has 60 contact points, it is necessary to check 3840 connections between the contact pins of the test head and the contact points of the semiconductor chips. In conventional methods, a negative voltage is applied to the contact points of the semiconductor chips. Internally, the contact points of the semiconductor chips are connected to a respective protective diode that is forward-biased in the case of a negative voltage at the contact points. The electrically conductive connection between the contact point and the respective contact pin of the test head is ascertained by the current flowing through the protective diodes and the contact points.
However, if all of the semiconductor chips on a wafer are intended to be tested simultaneously, given 500 to 1000 semiconductor chips on a wafer it is necessary to check 30,000 to 60,000 electrically conductive connections. Otherwise, even functional semiconductor chips do not pass the subsequent tests and are qualified as unusable.
The electrically conductive connection between the contact points of the semiconductor chips and the test pins of the test head cannot readily be checked by using the conventional methods.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for checking the electrically conductive connection between a large number of contact points of a wafer and the mating contacts of a test head.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for checking a conductive connection between contact points of semiconductor chips formed on a wafer and mating contacts of a test head. The method includes steps of: connecting functionally identical contact points of the semiconductor chips in columns using column lines configured in the test head; outputting test signals, which are temporally offset, in rows from the semiconductor chips to the column lines; and detecting and evaluating the test signals, which are temporally offset, from the column lines.
In accordance with an added feature of the invention, the method includes steps of: initially, connecting the contact points of the semiconductor chips to shift registers; and connecting the contact points in rows to a respective selection signal line.
In accordance with an additional feature of the invention, the method includes steps of: generating a test bit in each first storage cell of the shift registers by resetting the shift registers; applying a selection signal having a beginning that is temporally offset by rows; and shifting each test bit row by row to outputs of the shift registers, such that when each test bit arrives at the outputs of the shift registers, test signals are output to the column lines using driver circuits.
In accordance with another feature of the invention, the method includes steps of: placing the contact points in a high-impedance state if no test signal is present at the contact points.
In accordance with a further feature of the invention, the method includes steps of: connecting the contact points to a test signal line; and applying a test signal to the test signal line, and feeding the test signal in rows, one after another, to the column lines.
In accordance with a further added feature of the invention, the method includes steps of: using switching elements to connect rows of the contact points of the semiconductor chips to a plurality of test signal lines; and activating the switching elements using a respective selection contact point of the semiconductor chips.
In accordance with a further additional feature of the invention, the method includes using some of the column lines as the test signal lines.
In the inventive method, the electrically conductive connection between the contact points and the mating contacts of the test head is tested sequentially row by row. It suffices, therefore, for the test signals running on the column lines to be detected and evaluated. Therefore, only one evaluation circuit per column line is required for carrying out the method. Therefore, the technical outlay for carrying out the method is kept within acceptable limits.
In a preferred embodiment of the invention, the contact points of the semiconductor chips are connected to shift registers, that are connected row by row to switching signal lines. By applying switching signals to the switching signal lines, test bits in the shift registers are shifted row by row in a temporally offset manner to the output of the shift registers. Upon the application of a test bit, a test signal is output to the column lines using a driver circuit. In this refinement of the method, only two additional contact points for feeding in the switching signal and for resetting the shift registers are required at the semiconductor chips. This method can then be used to test all of the remaining contact points of the semiconductor chips independently of their function.
In a further preferred embodiment of the invention, the contact points are connected to test signal lines via which a test signal is subsequently fed row by row one after the other into the column lines.
In order to connect the contact points to the internal test signal line and in order to feed the test signals into the test signal line, at least three contact points are required.
In return, however, the shift registers assigned to the contact points can be dispensed with.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for checking a conductive connection between contact points, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5315553 (1994-05-01), Morris
patent: 5726920 (1998-03-01), Chen et al.
patent: 5956280 (1999-09-01), Lawrence
patent: 6622103 (2003-09-01), Miller
Greenberg Laurence A.
Infineon - Technologies AG
Le Vu A.
Mayback Gregory L.
Stemer Werner H.
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