Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-26
2004-03-16
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S057000, C257S066000, C257S072000, C257S347000, C257S401000, C257S622000
Reexamination Certificate
active
06707107
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of deforming a resist pattern to be used for forming a semiconductor device, and more particularly to a method of improving the accuracy in the quantity of deformation of an original resist pattern or improving a highly accurate control to a pattern shape of a reflow-deformed resist pattern.
2. Description of the Related Art
A conventional well known method of deforming the original resist pattern is a re-flow process by heating the original resist pattern. A quantity of deformation of the resist pattern or a difference in size of the deformed resist pattern from the original resist pattern is relatively small, for example, in the range of 0.5 micrometers to 3 micrometers.
Another conventional well known method of deforming the original resist pattern is to dip the original resist pattern into chemicals or expose the original resist pattern to a steam containing chemicals so that the chemicals osmose into the original resist pattern, whereby the original resist pattern is dissolved and deformed. A quantity of deformation of the resist pattern or a difference in size of the deformed resist pattern from the original resist pattern is relatively large, for example, in the range of 5 micrometers to 20 micrometers.
A high accuracy in the quantity of deformation of the resist pattern is desired. In order to obtain the high accuracy in quantity of the deformation, a highly accurate control to the quantity of deformation of the resist pattern is essential.
A conventional method of forming a thin film transistor utilizes the original resist pattern and the deformed resist pattern.
FIG. 1A
is a fragmentary plan view of a thin film transistor of a first step involved in conventional sequential fabrication processes.
FIG. 1B
is a fragmentary cross sectional elevation view of a thin film transistor shown in
FIG. 1A
, taken along a
1
B-
1
B line.
FIG. 2A
is a fragmentary plan view of a thin film transistor of a second step involved in conventional sequential fabrication processes.
FIG. 2B
is a fragmentary cross sectional elevation view of a thin film transistor shown in
FIG. 2A
, taken along a
2
B-
2
B line.
FIG. 3A
is a fragmentary plan view of a thin film transistor of a third step involved in conventional sequential fabrication processes.
FIG. 3B
is a fragmentary cross sectional elevation view of a thin film transistor shown in
FIG. 3A
, taken along a
3
B-
3
B line.
FIG. 4A
is a fragmentary plan view of a thin film transistor of a fourth step involved in conventional sequential fabrication processes.
FIG. 4B
is a fragmentary cross sectional elevation view of a thin film transistor shown in
FIG. 4A
, taken along a
4
B-
4
B line. A thin film transistor is formed over an insulating substrate
301
.
With reference to
FIGS. 1A and 1B
, a metal layer is formed on a top surface of an insulating substrate
301
. The metal layer is then patterned to form a gate electrode
302
. A gate insulating film
303
is formed over the top surface of the insulating substrate
301
and over the gate electrode
302
. An amorphous silicon film
304
is formed over the gate insulating film
303
. An n+-type amorphous silicon film
305
is formed over the amorphous silicon film
304
. A metal layer
306
is formed over the n+-type amorphous silicon film
305
.
Thick resist masks
318
and thin resist masks
328
are selectively formed over the metal layer
306
. The thick resist masks
318
are adjacent to a channel region
315
. The thick resist masks
318
separates the thin resist masks
328
from the channel region
315
. The thick resist masks
318
have a thickness of about 3 micrometers. The thin resist masks
328
have a thickness of about 0.2-0.7 micrometers. Each pair of the thick resist mask
318
and the thin resist mask
328
comprises a unitary-formed resist mask which varies in thickness.
With reference to
FIGS. 2A and 2B
, a first anisotropic etching process is carried out by using the thick and thin resist masks
318
and
328
for selectively etching the metal layer
306
and the n+-type amorphous silicon film
305
, whereby the remaining parts of the n+-type amorphous silicon film
305
become a source side ohmic contact layer
310
and a drain side ohmic contact layer
311
, and further the remaining parts of the metal layer
306
become a source electrode
313
and a drain electrode
314
.
A plasma ashing process is carried out in the presence of O
2
plasma for reducing the thickness of the resist masks, whereby the thin resist masks
328
are removed, while the thick resist masks
318
remain with a reduced thickness. These thickness-reduced resist masks
318
will hereinafter be referred to as residual resist masks
338
. The residual resist masks
338
are adjacent to the channel region
315
. These residual resist masks
338
provide the original resist patterns.
With reference to
FIGS. 3A and 3B
, the residual resist masks
338
are exposed to a steam for 1-3 minutes, wherein the steam contains an organic solvent, whereby the organic solvent gradually osmose into the residual resist masks
338
as the original resist patterns, so that the original resist pattern is dissolved and re-flowed, resulting in a reflow-deformed resist pattern
348
being formed. The reflow-deformed resist pattern
348
extends to the channel region
315
and outside regions of the residual resist masks
338
as the original resist patterns.
In the re-flow process, the residual resist masks
338
as the original resist patterns are inwardly re-flowed toward the channel region
315
and the re-flowed residual resist masks
338
come together over the channel region
315
. An interconnection
302
′ connected to the gate electrode
302
extends in a parallel direction to the line
3
B-
3
B. This interconnection
302
′ forms a step-like barrier wall
317
-
a
to stop the reflow of the re-flowed residual resist masks
338
, wherein the step-like barrier wall
317
-
a
extends in the parallel direction to the line
3
B′-
3
B. A further step-like barrier wall
317
-
b
is present, which extends in a perpendicular direction to the
3
B-
3
B line.
For this reason, the reflow of the residual resist masks
338
is stopped but only in two directions by the step-like barrier walls
317
-
a
and
371
b
. The reflow of the residual resist masks
338
is free and not limited in the remaining directions. It is difficult to control the reflow of the residual resist masks
338
in the remaining directions due to the absence of any re-flow restrictor such as the step-like barrier walls
317
-
a
and
371
b
. This means it difficult to control the pattern shape of the reflow-deformed resist mask
348
.
With reference to
FIGS. 4A and 4B
, a second anisotropic etching process is carried out by use of the reflow-deformed resist mask
348
and the source and drain electrodes
313
and
314
as masks for selectively etching the amorphous silicon film
304
, whereby the remaining part of the amorphous silicon film
304
becomes an island layer
324
. A pattern shape of the island layer
324
is defined by the reflow-deformed resist mask
348
in combination with additional masks of the source and drain electrodes
313
and
314
. The used reflow-deformed resist mask
348
is removed. As a result, a reverse staggered thin film transistor is formed.
As described above, the pattern shape of the island layer
324
is defined by the reflow-deformed resist mask
348
in combination with additional masks of the source and drain electrodes
313
and
314
. Further, it is difficult to control the reflow of the residual resist masks
338
in the remaining directions due to the absence of any re-flow restrictor such as the step-like barrier walls
317
-
a
and
371
b
. It is difficult to control the pattern shape of the reflow-deformed resist mask
348
. This means it difficult to control the pattern shape of the island layer
324
. The island layer
324
of amorphous silicon underlies th
Eckert George
NEC LCD Technologies Ltd.
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