Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-06-26
2004-08-31
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S566000, C257S579000
Reexamination Certificate
active
06784499
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device serving as a protecting element for protecting a semiconductor integrated circuit against surge voltage, i.e., electrostatic discharge (referred to as ESD).
2. Description of the Background Art
As a protecting element for protecting a semiconductor integrated circuit against surge voltage (i.e., ESD), it is conventionally known that an avalanche diode is interposed between an input/output terminal and a ground terminal.
For example, Japanese Patent Application Laid-open No. 548007 (1993), column 4 and FIG. 2, discloses an avalanche diode serving as an ESD protecting device which has a cathode connected to an input/output terminal side and an anode connected to the ground.
The above conventional circuit arrangement causes a breakdown of the avalanche diode when a surge voltage having positive (i.e., plus) polarity is applied to the input/output terminal, thereby absorbing the surge voltage and preventing the semiconductor integrated circuit which is connected to the input/output terminal from being broken.
The above arrangement is for a conventional ESD protecting mechanism. When a surge voltage enters into the input/output terminal, the avalanche diode needs to surely cause a breakdown so that the voltage level decreases down to a safe zone for internal elements of the semiconductor integrated circuit. To this end, a serial resistance component of the avalanche diode must be set to several ohms. However, the avalanche diode has a large internal resistance and accordingly a large area is required.
Furthermore, it may be possible to employ a thyristor element in addition to the avalanche diode. However, if the current continuously flows even after the thyristor element latches in response to the surge voltage, the thyristor will continuously turn on. Such a circuit arrangement cannot be applied to an output protecting circuit or a comparable circuit having lower circuit impedance.
Considering the recent trends that semiconductor integrated circuits are required to realize reduction of power consumption and downsizing, it is not preferable to employ the above-described conventional protecting element because of its large internal resistance and the required large area which lead to increase of costs. This conventional protecting element does not suit for an output protecting circuit or a comparable circuit having lower circuit impedance.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor device which is capable of assuring sufficient durability, in cost evaluation, against surge voltage when it is applied to a semiconductor integrated circuit which is compact in size and low in power consumption or applied to a semiconductor integrated circuit which is non-expensive.
To accomplish the above and other related objects, the present invention provides a first semiconductor device interposed between an input/output terminal and a ground terminal of a semiconductor integrated circuit, and serving as a protecting element for protecting the semiconductor integrated circuit against electrostatic discharge. The first semiconductor device includes an emitter electrode provided on a first main surface of a semiconductor substrate. A P-type base region is disposed in a surface of the first main surface and containing P-type impurities. An N-type emitter region, selectively disposed in a surface of the P-type base region, contains N-type impurities at a relatively higher concentration, and contacts with the emitter electrode. A base contact region is selectively disposed in a surface of the P-type base region, and is spaced from the N-type emitter region with a spatial clearance. The base contact region contains P-type impurities at a relatively higher concentration. A base electrode is disposed on the base contact region. An N-type collector region, disposed in a surface of the second main surface, contains N-type impurities at a relatively higher concentration and electrically contacts with a collector electrode. The emitter electrode is connected to the input/output terminal.
The base electrode and the collector electrode are connected to the ground potential. A main current flows in the direction normal to the main surface of the semiconductor substrate. This means that a vertical NPN transistor is used as a protecting element for protecting the semiconductor integrated circuit. The surge voltage can be suppressed. Temperature rise of the protecting element can be limited to a low level.
Furthermore, when the terminal current exceeds a predetermined value, the base-collector junction becomes a forward bias. The conductivity modulation will appear in an N-type collector region having a lower purity concentration. The resistance component decreases. Accordingly, the element, even it has a smaller element area, is not broken when it is subjected to a large current flowing due to the ESD surge. Thus, an economical protecting element is obtained even it has a smaller element area.
Furthermore, no thyristor element is required. In other words, the semiconductor device no longer encounters with a problem that the current continuously flows after the thyristor element latches in response to the surge voltage. In this respect, the semiconductor device of this invention can be applied to an output protecting circuit or a comparable circuit having lower circuit impedance.
The present invention provides a second semiconductor device interposed between an input/output terminal and a ground terminal of a semiconductor integrated circuit, and serving as a protecting element for protecting the semiconductor integrated circuit against electrostatic discharge. The second semiconductor device includes first and second NPN transistors and a PNP transistor. The first and second NPN transistors have emitters being commonly connected. The first NPN transistor has a collector and a base connected to the input/output terminal. The second NPN transistor has a collector and a base electrode connected to the ground terminal. The PNP transistor has a base commonly connected to the emitters of the first and second NPN transistors, an emitter connected to the input/output terminal, and a collector connected to the ground terminal.
This semiconductor device is used as a protecting element for protecting a semiconductor integrated circuit. The surge voltage can be suppressed. Temperature rise of the protecting element can be limited to a low level.
The present invention provides a third semiconductor device interposed between an input/output terminal and a ground terminal of a semiconductor integrated circuit, and serving as a protecting element for protecting the semiconductor integrated circuit against electrostatic discharge. The third semiconductor device includes an NPN transistor, a PNP transistor and a diode. An emitter of the NPN transistor, a base of the PNP transistor, and a cathode of the diode are commonly connected. An anode of the diode and an emitter of the PNP transistor are connected to the input/output terminal. A collector and a base of the NPN transistor are connected to the ground terminal, and a collector of the PNP transistor is connected to the ground terminal.
Hole injection easily occurs via a diode at a connecting portion between the emitter of the NPN transistor and the base of the PNP transistor. Due to the thyristor action, temperature rise can be further suppressed to a lower level.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4994874 (1991-02-01), Shimizu et al.
patent: 5223737 (1993-06-01), Canclini
patent: 5334886 (1994-08-01), Chuang
patent: 5452171 (1995-09-01), Metz et al.
patent: 5471082 (1995-11-01), Maeda
patent: 5780905 (1998-07-01), Chen et al.
patent: 5789785 (1998-0
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