Semiconductor memory device with detection circuit

Details Semiconductor memory device with detection circuit Semiconductor memory device with detection circuit

2002-07-24

2004-08-10

Lam, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

23

Reexamination Certificate

active

06775190

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capturing data in response to a data strobe signal.
2. Description of the Background Art
A progress for a high information transmitting rate in information industry in recent years is also requested in the domain of a dynamic random access memory (hereinafter referred to as DRAM.
In such circumstances, in order to achieve supply and reception of data at a high rate, a double data rate synchronous dynamic random access memory (DDR SDRAM) has been adopted. DDR SDRAM can input/output data at a data rate twice that of a clock signal in synchronism with leading and trailing edges of a clock signal. In DDR SDRAM, an internal operation thereof is controlled with a clock signal. In a case where data is captured, the data is captured using a data strobe signal DQS inputted externally.
As a result, DDR SDRAM has a requirement to synchronize the data captured in synchronism with data strobe signal DQS, further, with a clock signal.
FIG. 25
is a block diagram showing a configuration of a data processing system using DDR SDRAM.
Referring to
FIG. 25
, the data processing system
1
includes a controller
2
and plural DIMMs
3
each constituted of DDR SDRAM.
Controller
2
controls all of processing system
1
. Controller
2
outputs clock signal CLK for controlling each of DIMMs
3
. Furthermore, controller
2
outputs data strobe signal DQS that is used when each DDIM
3
captures data.
While clock signal buses
4
are provided to respective DIMMs
3
, a data strobe signal bus
5
is provided as a common bus with DIMMs
3
.
As a result, a phase difference arises between clock signal CLK inputted to each DIMM and data strobe signal DQS. That is, while clock signal CLK inputted to each DIMM and clock signal have the same input timing as each other, a phase shift occurs on the side of data strobe signal DQS inputted to each DIMM. To DIMM
3
closest to controller
2
, data strobe signal DQS is inputted in timing earlier than clock signal CLK, while to DIMM
3
farthest from controller
2
, data strobe signal is inputted in timing later than clock signal CLK.
Further detailed description will be given of such a shift in phase.
FIG. 26
is a block diagram showing a configuration of a data input circuit in DDR SDRAM.
Referring to
FIG. 26
, a data input circuit
10
includes: a data strobe signal DQS synchronization circuit
12
and a clock signal CLK synchronization circuit.
Data strobe signal DQS synchronization circuit
12
includes latch circuits L
1
to L
5
transmission gates TM
1
to TM
4
and an inverter IV
21
.
Latch circuits L
1
to L
5
receive data strobe signal DQS at the clock terminals. Latch circuit L
1
receives an internal data signal DQ at the input terminal when data strobe signal DQS is at L level. Furthermore, latch circuit L
1
latches internal data signal DQ having received at the input terminal thereof to output a signal &phgr;A
0
when data strobe signal DQS is at H level.
Latch circuit L
2
receives signal &phgr;A
0
when data strobe signal DQS is at H level. Furthermore, latch circuit L
2
latches signal &phgr;A
0
to output a signal &phgr;A
1
when data strobe signal DQS is at L level.
Latch circuit L
4
receives internal data signal DQ when data strobe signal DQS is at H level. Furthermore, latch circuit L
4
latches internal data signal DQ having received at the input terminal thereof to output a signal &phgr;B
1
when data strobe signal DQS is at L level.
Transmission gates TM
1
to TM
4
are each constituted of a P channel MOS transistor and an N channel MOS transistor.
Transmission gate TM
1
is connected between latch circuit L
2
and latch circuit L
3
. An output signal of inverter IV
21
is inputted to the gate of the P channel MOS transistor in transmission gate TM
1
. Furthermore, an address signal ADD externally inputted is inputted to the gate of the N channel MOS transistor in transmission gate TM
1
.
Transmission gate TM
2
is connected between latch circuit L
2
and latch circuit L
5
. The output signal of inverter IV
21
is inputted to the gate of the N channel MOS transistor in transmission gate TM
2
. Furthermore, address signal ADD is inputted to the gate of the P channel MOS transistor in transmission gate TM
2
.
Transmission gate TM
3
is connected between latch circuit L
4
and latch circuit L
3
. The output signal of inverter IV
21
is inputted to the gate of the N channel MOS transistor in transmission gate TM
3
. Furthermore, address signal ADD is inputted to the gate of the P channel MOS transistor in transmission gate TM
3
.
Transmission gate TM
4
is connected between latch circuit L
4
and latch circuit L
5
. The output signal of inverter IV
21
is inputted to the gate of the P channel MOS transistor in transmission gate TM
4
. Furthermore, address signal ADD is inputted to the gate of the N channel MOS transistor in transmission gate TM
4
.
Note that inverter IV
21
receives address signal ADD to invert the signal and to output the inverted signal. When address signal ADD is at H level, transmission gates TM
1
and TM
4
are turned on while transmission gates TM
2
and TM
3
are turned off. Accordingly, signal &phgr;A
1
outputted from latch circuit L
2
is inputted to latch circuit L
3
. Furthermore, signal &phgr;B
1
outputted from latch circuit L
4
is inputted to latch circuit L
5
.
When address signal ADD is at L level, transmission gates TM
2
and TM
3
are turned on while transmission gates TM
1
and TM
4
are turned off. Accordingly, signal &phgr;A
1
outputted from latch circuit L
2
is inputted to latch circuit L
5
. Furthermore, signal &phgr;B
1
outputted from latch circuit L
4
is inputted to latch circuit L
3
.
As a result, address signal ADD changes a transmission path of internal data signal DQ.
Latch circuit L
3
receives a signal at the input terminal when data strobe signal DQS is at L level. Furthermore, latch circuit L
3
latches the signal having received at the input terminal to output a signal &phgr;A
2
when data strobe signal DQS is at H level.
Latch circuit L
5
receives a signal at the input terminal when data strobe signal DQS is at L level and latches the signal having received at the input terminal to output a signal &phgr;B
2
when data strobe signal DQS is at H level.
Clock signal synchronization circuit
13
includes latch circuits L
6
, L
7
, L
22
and L
23
. Latch circuit L
6
receives signal &phgr;A
2
when clock signal CLK is at L level and latches signal &phgr;A
2
and output the signal to latch circuit L
22
when clock signal CLK is at H level. Latch circuit L
22
receives an output signal of latch circuit L
6
when clock signal CLK is at H level and latches an output signal of latch circuit L
6
to output the signal as a signal &phgr;A
4
to a circuit in DDR SDRAM when clock signal CLK is at L level.
Latch circuits L
7
and L
23
operate in a similar way to the cases of latch circuits L
6
and L
22
. Latch circuit L
7
receives signal &phgr;B
2
at the input terminal thereof and latch circuit L
23
outputs signal &phgr;B
4
to a circuit in DDR SDRAM.
FIG. 27
is a timing chart showing operation of data input circuit
10
of FIG.
26
.
Referring to
FIG. 27
, in DDR SDRAM, data DQ is in synchronism with rising edge and falling edges of data strobe signal DQS. A data signal DQ
1
is in synchronism with the rising edge of data strobe signal DQS. Data signal DQ
1
includes a set-up time tDS and a hold time DH relative to data strobe signal DQS. A data signal DQ
2
is in synchronism with the falling edge of data strobe signal DQS. Data signal DQ
2
includes a set-up time tDS and a hold time DH relative to data strobe signal DQS similar to data DQ
1
.
Now, on the assumption that address signal ADD is at H level, description will be given of operation in data input circuit
10
.
First of all, description will be given of operation in latch circuit L
1
in data input circuit
10
.
Just before time t1, data strobe signal DQS is at L

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