Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-10-17
2004-10-05
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S328000, C257S335000, C438S664000, C438S665000, C438S305000, C438S306000
Reexamination Certificate
active
06800901
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a process for the selective formation of salicide on active areas of MOS devices.
BACKGROUND OF THE INVENTION
In the field of semiconductor integrated circuits, it is known to use composite materials comprising silicon and a transition metal e.g., Ti, Co and the like, called silicides, for forming layers having a relatively small resistivity.
In particular, silicides are formed on active areas of MOS transistors for reducing the resistance of source and drain diffusion regions, when these regions extend significantly.
A known method for forming a silicide layer on the active areas of MOS transistors provides for forming a gate of the transistor, comprising a gate oxide layer and a polysilicon layer, introducing in the silicon a dopant for the formation of the source and drain diffusion regions of the transistors, and then depositing, over the whole surface of the silicon, a transition metal, such as Ti and Co, and performing a thermal process during which the transition metal reacts with the silicon for creating the silicide.
Since the silicide layer which forms on the active area of the MOS transistor is automatically aligned with the gate, the process is called “self-aligned-salicidation”, shortly “salicidation”, and the layer thus obtained is correspondingly called “salicide”.
A drawback in the formation of salicide is due to the consumption of part of the silicon at the interface during the reaction between silicon and the transition metal.
In addition, during the salicidation process part of the dopant in the underlying silicon is absorbed.
For normal MOS transistors these effects are not particularly harmful, thanks to the substantial depth of the source and drain diffusion regions and their high doping level.
However, in some applications such as those providing for forming, by means of the “Drain-Extension” (DE) technique, N- or P-channel MOS transistors for high voltage (HV), the source and drain diffusion regions of the MOS transistors, respectively, comprise a first region, lightly doped and shallow, and a second region, more heavily doped and of greater thickness, connected to the first region. For the fabrication of such transistors, after the formation of the gate a relatively small dose of dopant is introduced in the silicon, respectively of N type for the N-channel transistors and of P-type for the P-channel ones, so as to form said first lightly doped regions of the source and drain diffusion regions which are automatically aligned with the gate. Successively, a high dose of dopant, of N or P type, is selectively implanted by way of a mask covering the gate and extending over the first lightly doped regions.
In order to form salicide over the source and drain diffusion regions of the transistors, a transition metal is then deposited over the whole silicon surface, and there is performed a thermal process.
The salicide thus forms both over the more heavily doped and deeper regions of the source and drain diffusion regions, where as already mentioned it does not cause particular problems, and over the more lightly doped and shallower regions of the source and drain diffusion regions.
In such lightly doped regions, due to their low doping level and their small thickness, the absorption of dopant by the salicide and the consumption of part of the silicon for the formation of salicide can cause problems, for example, the short-circuit of the salicide with the substrate.
SUMMARY OF THE INVENTION
An object of the present invention is that of providing a process of formation of salicide over active areas of MOS transistors, particularly of the type formed by means of the “drain-Extension” technique, allowing one to overcome the above-mentioned problems, in particular avoiding deterioration of existing lightly doped regions of the source and drain diffusions regions.
In an embodiment of the present invention, there is provided a process for forming salicide on active areas of MOS transistors, each comprising a gate and respective source and drain regions comprising each a first lightly doped sub-region near the gate and a second highly doped sub-region spaced apart from the gate, wherein the salicide is formed selectively only over said second highly doped sub-regions of the source and drain regions of the MOS transistors.
The salicide is formed by depositing over the whole surface of a semiconductor wafer a layer of a transition metal, but protecting (masking) those regions of the wafer where the salicide is not to be formed, in particular the first sub-regions of the source and drain regions of the MOS transistors, in such a way as the transition metal is in contact with the silicon over said second sub-regions but not over the first sub-regions. By submitting the wafer to a thermal process, the layer of transition metal reacts to form the salicide only in the regions where it is deposited directly over the silicon (mono- or poly-crystalline) while remaining unmodified in the other regions from which it can be removed.
Advantageously, for depositing the transition metal over said second sub-regions the same mask is used as that used for the selective introduction of the dopant for the formation of the second sub-regions.
These and other features and advantages of the present invention will be made apparent by the following detailed description of embodiments thereof, illustrated as non-limiting examples in the annexed drawings.
REFERENCES:
patent: 4735680 (1988-04-01), Yen
patent: 4855247 (1989-08-01), Ma et al.
patent: 4949136 (1990-08-01), Jain
patent: 4988643 (1991-01-01), Tsou
patent: 5086017 (1992-02-01), Lu
patent: 5120673 (1992-06-01), Itoh
patent: 5200351 (1993-04-01), Hadjizadeh-Amini
patent: 5283449 (1994-02-01), Ooka
patent: 5328863 (1994-07-01), Cappelletti et al.
patent: 5389809 (1995-02-01), Haken et al.
patent: 5439839 (1995-08-01), Jang
patent: 5508217 (1996-04-01), Sawada
patent: 5521411 (1996-05-01), Chen et al.
patent: 5550073 (1996-08-01), Hong
patent: 5589423 (1996-12-01), White et al.
patent: 5605854 (1997-02-01), Yoo
patent: 5658811 (1997-08-01), Kimura et al.
patent: 5753557 (1998-05-01), Tseng
patent: 5759897 (1998-06-01), Kadosh et al.
patent: 5759901 (1998-06-01), Loh et al.
patent: 5763285 (1998-06-01), Yang
patent: 5930631 (1999-07-01), Wang et al.
patent: 5933740 (1999-08-01), Chapman
patent: 0 334 761 (1989-09-01), None
patent: 0 607 820 (1994-07-01), None
patent: 07-233042 (1997-03-01), None
Pfiester et al., “A Cobalt Salicide CMOS Process with TiN-Strapped Polysilicon Gates,”IEEE Electron Device Letters, 12(6): 350-352, 1991.
Clementi Cesare
Moroni Maurizio
Erdem Fazli
Jorgenson Lisa K.
STMicroelectronics S.r.l.
Tarleton E. Russell
LandOfFree
Process for the selective formation of salicide on active... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for the selective formation of salicide on active..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for the selective formation of salicide on active... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3288035