Inter-signal proximity verification in an integrated circuit

Details Inter-signal proximity verification in an integrated circuit Inter-signal proximity verification in an integrated circuit

2002-07-19

2004-10-19

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C703S015000

Reexamination Certificate

active

06807657

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention relates to integrated circuit design and, more particularly, to techniques for reducing crosstalk in an integrated circuit.
2. Related Art
Integrated circuits (ICs) are becoming increasingly large and complex, typically including millions of individual circuit elements such as transistors and logic gates. As a result of this increased size and complexity, IC designers are increasingly using electronic design automation (EDA) software tools to assist with IC design. Such tools help to manage the complexity of the design task in a variety of ways, such as by allowing ICs to be designed hierarchically, thereby enabling the design to be divided into modules and enabling the design task to be divided among multiple designers in a manner that limits the complexity faced by any one designer.
Various hardware description languages (HDLs) have been developed which allow circuit designs to be described at various levels of abstraction. A description of a circuit according to an HDL (referred to herein as an “HDL model” of the circuit) may, for example, describe a particular circuit design in terms of the layout of its transistors and interconnects on an IC, or in terms of the logic gates in a digital system. Descriptions of a circuit at different levels of abstraction may be used for different purposes at various stages in the design process. HDL models may be used for testing circuits and circuit designs, as well as for fabricating the circuits themselves. The two most widely-used HDLs are Verilog and VHDL (Very High Speed Integrated Circuits (VHSIC) Hardware Description Language), both of which have been adopted as standards by the Institute of Electrical and Electronics Engineers (IEEE). VHDL became IEEE Standard 1076 in 1987 and Verilog became IEEE Standard 1364 in 1995.
EDA tools are typically capable of converting a functional HDL description of a circuit design into a specific circuit implementation. The specific circuit implementation may be represented by a “netlist,” which identifies both the elements of the circuit and the interconnections among them. In general, a netlist describes the circuit design in terms of nodes and edges. Each node represents a circuit element and each edge represents an interconnection between two circuit elements. Netlists may describe circuits at various levels of abstraction. A netlist may, for example, describe circuit elements in terms of specific structural components (such as resistors and transistors) or in terms of high-level “cells” that may be decomposed into specific structural components and/or other cells. A netlist may, for example, describe the connections between cells in terms of specific cell-to-cell pin connections.
EDA tools are typically capable of converting a netlist into a physical layout of the circuit. The layout process involves both “placement” (assigning specific coordinates in the circuit layout to each cell) and “routing” (wiring or connecting cells together). The layout produced thereby defines the specific dimensions and coordinates of the gates, interconnects, contacts, and other elements of the circuit. The layout may have multiple layers, corresponding to the layers of the circuit. The layout may be used to form a mask, which in turn may be provided to a foundry to fabricate the integrated circuit itself.
One stage in the process of IC design is package design, which refers to the design of substrates (packages) for interconnecting layers of the IC. An IC typically includes multiple packages interconnected in layers. Each package, in turn, may include multiple layers (also referred to as “planes”). Packages within a single IC may be composed of varying materials having varying electrical properties. Individual signal nets (also referred to herein simply as “nets”) in the IC may be distributed across multiple packages. A package design must ensure that signals in the IC have sufficient power and maintain sufficient signal integrity when passing from one layer of the IC to another. As used herein, the term “signal net” (or simply “net”) refers to a collection of conductors that are connected to form a complete circuit connecting at least one output to at least one input.
As with IC design more generally, various tools exist for automating aspects of IC package design. Such tools typically provide a graphical user interface through which package designers may visually design the IC package in three dimensions. For example, referring to
FIG. 1
, a prior art package design system
100
is shown in which a human package designer
116
creates and modifies a model
102
of an integrated circuit package using a package design tool
104
. The package designer
116
may, for example, use a keyboard
114
or other input device to provide input
108
to the package design tool
104
, in response to which the package design tool
104
may modify the package model
102
and display a graphical representation
106
of the package model
102
(or of particular layers therein) on a display monitor
112
. The graphical representation
106
typically displays signal traces as lines on a two-dimensional grid.
The package model
102
may include, for example, information specifying the name, location, and size of each signal trace, ground metal, via, and other elements of the package model
102
. The package model
102
is typically stored in a database file in a computer system.
One example of the package design tool
104
is Advanced Package Designer (APD), available from Cadence Design Systems, Inc. of San Jose, Calif. APD is a software program which allows the package designer
116
to model the physical, electrical, and thermal characteristics of the package substrate. An APD package design database (e.g., the package model
102
) may be provided to a foundry to be used directly as manufacturing input for fabrication of the designed package.
It is common for package designs to include distinct signal layers and ground layers. For example, package model
102
includes layers
104
a-c
, including ground layer
104
a
, signal layer
104
b
, and ground layer
104
c
. Although package models typically contain additional layers, only the three layers
104
a-c
are shown in
FIG. 1
for ease of illustration. A signal layer (such as Layer
104
b
) typically includes only signal traces (also referred to as signal lines), while a ground layer (such as Layer
104
a
or
104
c
) typically includes only ground metal, typically arranged either in a grid or in a solid plane. Signal layers and ground layers are often arranged so that each signal layer is located between two ground layers. It is important that there be ground metal directly above or below each signal trace in a signal layer to ensure an adequate ground return path for each signal trace.
It is also important that signal traces in the package model
102
not be too close to each other. This is referred to herein as a “minimum inter-signal spacing requirement.” Closely-spaced signal traces introduce crosstalk in each other, thereby reducing signal integrity. Some package design tools do not automatically verify that signal traces are spaced sufficiently far from each other. In such cases the human package designer
116
may need to manually verify that the minimum inter-signal spacing requirement is met for all signal traces in the package model
102
. This is a tedious, time-consuming, and error-prone process.
To verify that inter-signal spacing requirements are met, the package designer
116
may visually inspect the graphical representation
106
. Signal traces may, for example, be graphically represented as lines on the display monitor
112
. Verifying inter-signal spacing by visually inspecting the graphical package representation
106
may be difficult due to the large number and close spacing of signal traces.
Additionally or alternatively, the package design tool
104
may generate textual package property reports
110
which list various properties of the package model
102
, such as the locations and lengths of s

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