Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-10-24
2004-11-02
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C438S617000, C257S723000, C257S758000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06813756
ABSTRACT:
The present patent application claims the benefit of earlier Japanese Patent Application No. H11-327370 filed Nov. 17, 1999, the disclosure of which is entirely incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a technique of automatic layout design applied to CAD for placement and routing. The invention also relates to a mask set and a semiconductor integrated circuit manufactured by the automatic layout design technique, and to a recording medium storing the automatic layout program.
2. Description of the Related Art
Along with the progress of LSI technologies, the circuit scale becomes larger and larger, and consequently, which causes increase of an amount of logical design computation. Such logical design is carried out making use of computers, which is known as CAD (Computer Aided Design).
In designing interconnection of basic horizontal and vertical lines in the orthogonal coordinate system on CAD, horizontal and vertical lines often terminate at an intersection of two or more orthogonal lines. If the horizontal lines and the vertical lines are formed in different layers in an actual semiconductor device, a via hole must be formed at the terminal portions of the metal lines to connect the horizontal and vertical lines three-dimensionally. Accordingly, a connection pattern corresponds to the via hole must be defined at a terminal of horizontal and vertical lines on CAD.
In general, if two basic orthogonal lines having an ordinary width W terminate at an intersection, terminal processing is carried out to extend the ends of the orthogonal lines by W/2.
FIG. 1
shows an example of terminal processing of the basic orthogonal lines of the minimum width. In
FIG. 26A
, a horizontal line
801
and a vertical line
803
meet each other at a terminal. In a CAD system, only the intersection point at which the center lines
802
and
804
of the respective lines cross each other is recognized as an intersection
808
. The CAD does not recognize the overlap of two orthogonal lines at all.
If, in an actual semiconductor device, the horizontal line
801
is formed in a lower layer and the vertical line
802
is formed in an upper layer, these two lines must be connected three-dimensionally by a via contact. In this case, the CAD layout requires a connection pattern
805
(
FIG. 1C
) at the intersection of the two orthogonal lines
801
and
803
. The connection pattern
805
consists of a bottom metal
801
a
, which is a part of the end portion of the line
801
, a top metal
803
a
, which is a part of the end portion of the line
803
, and an opening
807
(hereinafter, referred to as a “cut”) for connecting the top and bottom metals
803
a
and
801
a.
In an example shown in
FIG. 1
, the CAD recognizes two lines crossing each other, and accordingly, it is possible to define the connection pattern
805
at the intersection recognized by the CAD. However, if the two lines terminate in the state shown in
FIG. 1A
, the overlapped area between the horizontal line
801
and the vertical line
803
is very small. If a via hole is formed in an actual integrated circuit based on the layout shown in
FIG. 1A
, the lines of the upper and lower layers can not be reliably connected.
To overcome this problem, the ends of the horizontal and vertical lines
801
and
803
are extended by W/2, as shown in
FIG. 1B
, so that the end portion of the vertical line
803
lies completely on top of the end portion of the horizontal line
801
. Then, the connection pattern
805
is placed on the overlapped area.
FIG. 1C
illustrates a connection pattern
805
and a side view of a via hole formed in an actual integrated circuit. The connection pattern
805
is square because it is placed at the intersection of two basic orthogonal lines.
FIG. 2
illustrates another conventional example of terminal processing of two orthogonal lines. In this case, two wider orthogonal lines meet each other and terminate at the junction. Although the wide lines are treated as special lines in CAD, both of the horizontal line
811
and the vertical line
811
are extended by W/2, so that the end portions of these lines completely overlap each other, like in FIG.
1
. Because the overlapped area is large, a connection pattern
805
having a plurality of cuts
817
is placed in the overlapped area.
It is easy for a CAD system to carry out the terminal processing to design interconnection consisting of only orthogonal lines in a orthogonal coordinate system, as shown in
FIGS. 1 and 2
.
However, as the configuration of semiconductor integrated circuits becomes finer and finer, a higher precision is required in every respect including a manufacture process and components of a semiconductor integrated circuit. In particular, a delay component caused by interconnection (or wiring) adversely affects the performance of the integrated circuit when the integrated circuit becomes finer. For this reason, it is an important subject how to reduce such delay in the integrated circuit.
Most of the delay components of interconnection are caused by a line resistance. The most effective way to reduce a line resistance is to reduce the line length. To this end, it has been proposed to use oblique lines, in addition to the basic orthogonal lines, to reduce the distance between two points in a semiconductor circuit. There is also a proposal to design a circuit layout using oblique lines on CAD. If using oblique lines in multi-layered integrated circuit, the shape and the forming process of via holes connecting basic orthogonal lines in a lower layer and oblique lines in an upper layer must be optimized.
The inventors of the present invention have proposed in Japanese Patent Application Nos. 10-176285 and 11-175930 a technique for greatly reducing a line resistance of oblique lines itself. This is achieved by setting the width and film thickness of the oblique line to {square root over (2)} times as large as those of the basic orthogonal lines. In these publications, the optimal shapes of via holes for connecting metal lines of different layers are also proposed in order to reliably guarantee the cross-sectional area of the cut. The inventors also proposed a tree-type clock supply path comprised of a combination of oblique lines and the basic orthogonal lines.
However, no proposal has been made on a terminal processing for treating a terminal junction of an oblique line and a horizontal (or vertical) line on CAD.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an automatic layout method, which allows a CAD system to easily carry out terminal processing for treating end portions of lines, including oblique lines.
It is another object of the invention to provide an exposure mask set formed by the automatic layout method and suitably used to manufacture a multi-layered integrated circuit with oblique interconnection.
It is still another object of the invention to provide a semiconductor integrated circuit having an oblique line configuration, which can achieve faster and more precise operations.
It is yet another object of the invention to provide a large scaled integrated circuit (LSI) having a clock supply structure utilizing oblique lines.
It is yet another object of the invention to provide an LSI, in which a plurality of blocks are integrated, each block being capable of operating fast and accurately, in synchronization with others.
It is yet another object of the invention to provide a method of manufacturing a semiconductor integrated circuit having an oblique interconnection structure.
It is yet another object of the present invention to provide a storage medium storing a program for executing an automatic layout method. By loading this program on a CAD, the CSD can generate a circuit layout using oblique lines with less data amount.
To achieve these objects, in one aspect of the invention, an automatic layout method used to, for example, CAD is provided. With this method, a first line having a first width is generated in a prescribed di
Igarashi Mutsunori
Ishioka Takashi
Minami Fumihiro
Mitsuhashi Takashi
Murakata Masami
Do Thuan
Gray Cary Ware & Freidenrich LLP
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