Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-07-01
2004-11-09
Nguyen, Thanh (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S301000
Reexamination Certificate
active
06815751
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to capacitor structures having increased capacitance that can be used as charge storage elements for various memory cells including dynamic random access memory (DRAM) cells. The present invention also relates to methods of fabricating such capacitor structures for use in various memory cells.
2. Background of the Invention
A memory cell in an integrated circuit (IC) includes a transfer device such as a transistor and an associated capacitor. The capacitor, which is typically formed in a portion of a trench, consists of a pair of conductive plates, i.e., electrodes, which are separated from each other by a node dielectric material. Information or data is stored in the memory cell in the form of charge accumulated on the capacitor. As the density of ICs with memory cells is increased, the area for the capacitor becomes smaller and the amount of charge the capacitor is able to accumulate is reduced. Thus, with less charge to detect, reading the information or data from the memory cell becomes much more difficult.
Dynamic random access memory (DRAM) cells are widely used in storing information because they can be implemented to provide an extraordinary number of memory cells in a relatively small area. Although various techniques are known for fabricating DRAM cells, planar DRAM processes have the benefit of low cost and easy integration with standard complementary metal oxide semiconductor (CMOS) processing. The major problem associated with planar capacitors is the inability to scale with technology generations. As cell sizes have decreased, the planar capacitor has not scaled accordingly due to tunneling current constraints. The gate dielectric thickness tends to be 2-3 generations behind. Therefore, to keep the cell capacitance high, the area of the planar capacitor cannot scale with the technology and thus dominates cell area.
One attempt to reduce the cell area, as well as the integration area required for each cell is disclosed, for example, in U.S. Pat. No. 6,087,214 to Cunningham. Specifically, the Cunningham disclosure provides a method for fabricating a memory cell which includes the steps of: selectively removing portions of a substrate using a patterned mask to simultaneously form a capacitor trench and an isolation trench which is at least partially around the capacitor trench; forming an oxide in both the isolation and capacitor trenches; selectively removing the oxide in the capacitor trench; doping portions of substrate so as to define the base and sidewalls of the capacitor; forming a thin capacitor dielectric on the exposed walls (including bottom and sidewalls) of the capacitor trench; and then filling the remaining portion of the capacitor trench with polysilicon.
Despite creating more cell capacitance, the process and structure disclosed in the Cunningham disclosure suffer an area penalty because an isolation trench is needed around the cell to provide cell-to-cell isolation. No method or structure is provided in the Cunningham disclosure that eliminates the isolation trench around the memory cell. As such, the process and structure disclosed in Cunningham fails to provide a capacitor structure for a memory cell having the combination of high cell capacitance and reduced cell area.
In view of the drawbacks mentioned above with prior art processes of fabricating memory cells having the combination of high cell capacitance and reduced cell area, there exists a need for providing a new and improved method for fabricating such memory cells.
BRIEF SUMMARY OF THE INVENTION
One object of the present invention is to provide a capacitor for a memory cell that has increased capacitance.
A further object of the present invention is to provide a high-capacitance capacitor for a memory cell array that maintains cell-to-cell isolation without the need of requiring isolation trench regions to surround each memory cell.
A yet further object of the present invention is to provide a high-capacitance capacitor for a memory cell that is fabricated using existing CMOS processing techniques.
An even further object of the present invention is to provide a high-capacitance capacitor for a memory cell that can be fabricated into either a bulk semiconductor substrate or a layered semiconductor substrate such as, for example, a silicon-on-insulator (SOI) substrate.
These and other objects and advantages are achieved in a first embodiment of the present invention by providing a capacitor design that uses standard CMOS processing plus one extra mask to partially recess isolation material from a plurality of isolation-filled trenches that are formed in a semiconductor substrate so as expose sidewalls of each of the holes. The amount of sidewall exposure can be modulated by the recess, such that more isolation material can be removed from the holes to further increase capacitance as technologies scale. To maximize the sidewall capacitance improvement, the inventive layout of the capacitor changes from a single square capacitor design (such as described in the Cunningham disclosure mentioned supra) to a multi-fingered capacitor.
In a second embodiment of the invention, the isolation-filled trenches are etched to remove all of the isolation fill in areas where the capacitors are to be formed. A subsequent etch is carried out to increase the depth of the trenches in these areas, and the bottoms of the etched trenches are implanted with dopant ions to provide isolation.
In a third embodiment of the invention, the isolation-filled trenches in an SOI substrate are etched to remove all the isolation fill in areas where the capacitors are to be formed. The etch is continued into the buried SOI oxide itself for enough time to provide sufficient depth for a capacitor while still leaving enough buried SOI oxide to provide isolation.
Accordingly, a first aspect of the present invention relates to a capacitor structure which is formed in a semiconductor substrate, e.g., bulk or layered, which comprises: a plurality of holes, each having a plurality of sidewalls and a bottom wall, located in a region of a semiconductor substrate in which a plurality of isolation filled trenches are absent, said holes having a depth proximate that of said plurality of isolation filled trenches; insulating material present in each hole on said plurality of sidewalls and bottom wall, wherein said insulating material is thicker on said bottom wall as compared to said plurality of sidewalls; and a conductor filling each of said holes.
In a second aspect, the present invention relates to a memory cell structure which includes at least the aforementioned first capacitor structure. Specifically, the inventive memory cell structure comprises: a transfer device located atop a surface of a semiconductor substrate; and a capacitor having an electrode coupled to said transfer device, said capacitor comprising: a plurality of holes, each having a plurality of sidewalls and a bottom wall, located in a region of a semiconductor substrate in which a plurality of isolation filled trenches are absent, said holes having a depth proximate that of said plurality of isolation filled trenches and are arranged to form a plurality of laterally extending portions having a plurality of sides and a bottom, insulating material present in each hole on said plurality of sidewalls and bottom wall, wherein said insulating material is thicker on said bottom wall as compared to said plurality of sidewalls, counter-dopant regions on the sides of said laterally extending portions, and a conductor filling each of said holes.
In a third aspect, the present invention relates to a capacitor structure having increased capacitance. The second capacitor structure of the present invention comprises: a plurality of holes, each having a plurality of sidewalls and a bottom wall, located in a region of a semiconductor substrate in which a plurality of isolation filled trenches are absent, said holes having a depth that is deeper than tha
Brown Jeffrey S.
Mann Randy W.
Canale Anthony J.
Nguyen Thanh
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