Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-10-18
2004-08-03
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S203000, C365S230080
Reexamination Certificate
active
06771553
ABSTRACT:
TECHNICAL FIELD
This invention relates to dynamic random access memories, and, more particularly, to a circuit and method for reducing the power consumed by such memories when operating in an auto-refresh mode.
BACKGROUND OF THE INVENTION
The power consumed by integrated circuits can be a critical factor in their utility in certain applications. For example, the power consumed by memory devices used in portable personal computers greatly affects the length of time they can be used without the need to recharge batteries powering such computers. Power consumption can also be important even where memory devices are not powered by batteries because it may be necessary to limit the heat generated by the memory devices.
In general, memory device power consumption increases with both the capacity and the operating speed of the memory devices. The power consumed by memory devices is also affected by their operating mode. A dynamic random access memory (“DRAM”), for example, will generally consume a relatively large amount of power when the memory cells of the DRAM are being refreshed because rows of memory cells in a memory cell array are then being actuated in the rapid sequence. Each time a row of memory cells is actuated, a pair of digit lines for each memory cell are switched to complementary voltages and then equilibrated, thereby consuming a significant amount power. As the number of columns in the array increases with increasing memory capacity, the power consumed in actuating each row increases accordingly. Power consumption also increases with increases in the rate at which the rows of memory cells are actuated. Thus, as the operating speed and capacity of DRAMs continues to increase, so also does the power consumed increase during refresh of memory cells in such DRAMs.
During a DRAM refresh, power is also consumed by components other than those in the memory cell array. For example, DRAM devices generally include a large number of input buffers to couple a large number of control and address lines to internal circuitry. While the DRAM is being refreshed, these input buffers continue to switch responsive to control and address signals applied to their respective inputs. However, during some refresh modes, control and address signals are not used by the DRAM. In an auto-refresh mode, for example, an auto-refresh command is applied to the DRAM. The DRAM thereafter internally performs a refresh operation for a predetermined period of time. During this period, the DRAM does not respond to control and address signals applied to its input buffers. However, the input buffers continue to switch during this time. Switching these large number of input buffers during an auto-refresh cycle wastes power because, as mentioned above, the signals coupled through the input buffers are not used during an auto-refresh cycle.
In the past, attempts have been made to minimize the power consumption of DRAMs during auto-refresh by removing power to all input buffers except input buffers for clock (“CLK”) and clock enable (“CKE”) signals. However, leaving the input buffer for the clock active causes the input buffer to consume a significant amount of power during the auto-refresh period since the input buffer toggles with each clock signal transition. Power could be significantly reduced by removing power to the input buffer for the clock signal during the auto-refresh period. But doing so could cause spurious commands to be registered at the conclusion of the auto-refresh period. As is known in the art, memory commands are typically registered by latching command signals into respective latches responsive to one or both edges of the clock signal. If a clock edge occurs during the time that the input buffers for the command signals are being re-powered after the auto-refresh period, a spurious command corresponding to the transitional states of the input buffers may be registered. Although care can be taken to avoid coupling clock signal transitions to a memory device until re-powering of the input buffers have been completed, a spurious clock signal transition may be generated. A spurious clock signal transition can be generated if the clock signal has a high logic level when the input buffer for the clock signal is re-powered. The spurious clock signal will then register whatever spurious command corresponds to the logic levels at the outputs of the input buffers for the command signals.
In the past, attempts have been made to reduce power during a self-refresh cycle by removing power from the input buffers during the self-refresh period. For a self-refresh command, spurious commands are avoided by first detecting a low-to-high transition of the CKE signal, which signifies the end of the self-refresh. However, the input buffers for the command and address signals are not re-powered at that time. Instead, the output of a small input buffer coupled to the CLK is examined to detect a high-to-low transition of the CLK signal. When the high-to-low transition of the CLK signal is detected, the input buffers for the command and address signals are re-powered so that they will not be in a transitional state by the time the next low-to-high transition of the CLK signal occurs, which is used to register the commands and addresses.
Although the approach described above does reduce power consumption during self-refresh without the risk of registering spurious commands and addresses, this approach is not suitable for use during an auto-refresh cycle. Unlike a self-refresh command, for which the controlling specification allows a delay of two CLK periods to exit the self-refresh cycle, the controlling specification for an auto-refresh command requires the DRAM to be able to register a command occurring on the very next rising edge of the CLK signal. However, the input buffers for the command and address signals may still be in a transitional state at that time, thereby causing spurious command or addresses to be registered.
One approach to minimizing power consumption during an auto-refresh cycle is to remove power from some of the command and address input buffers, but not the input buffers for the clock and clock enable signals, for a predetermined period after the start of an auto-refresh cycle. For example, if an auto-refresh cycle is expected to last 60 nanoseconds, the input buffers might be de-energized for the first 40 nanoseconds. Although this approach does reduce the power consumed during an auto-refresh cycle, it nevertheless still allows a significant amount power to be consumed during the period of time that the input buffers are energized. It is generally not possible to de-energize the input buffers for substantially the entire auto-refresh cycle because the input buffers must be re-powered well before the end of the auto-refresh cycle and the end of the refresh cycle cannot always be predicted with great accuracy. Thus, de-energizing the input buffers for a predetermined period at the start of each auto-refresh cycle still allows the DRAM to consume a significant amount of power.
There is therefore a need for a circuit and method that allows a more significant reduction in the power consumed by DRAMs during an auto-refresh cycle without risk of registering spurious commands or addresses.
SUMMARY OF THE INVENTION
A method and circuit reduces the power consumed by a dynamic random access memory (“DRAM”) during an auto-refresh. The DRAM includes a first set of input buffers through which command signals are coupled. The input buffers are disabled during auto-refresh so they do not consume power responding to signals applied to their inputs, and a plurality of command signals are biased to assert a predetermined memory command, such as a “no operation” command. When an internal auto-refresh timer times out, the bias is removed from the command signals, and the input buffers are enabled. In the event the DRAM receives a clock signal, an input buffer through which the clock signal is coupled may also be disabled during the auto-refresh. If so, the input buffer for the clock signal may be re-enabled b
Blodgett Greg A.
Cowles Timothy B.
Shirley Brian M.
Dorsey & Whitney LLP
Lebentritt Michael S.
Micro)n Technology, Inc.
Nguyen Hien
LandOfFree
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