Semiconductor memory device with proper sensing timing

Details Semiconductor memory device with proper sensing timing Semiconductor memory device with proper sensing timing

2004-02-26

2004-12-28

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S205000, C365S207000

Reexamination Certificate

active

06836426

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
The present application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2003-363370 filed on Oct. 23, 2003, with the Japanese Patent Office, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a ferroelectric memory in which the latch timing of a sense amplifier is adjusted.
2. Description of the Related Art
A ferroelectric memory (FRAM, FeRAM) is used as a memory medium for an IC card or the like due to the use of a ferroelectric capacity as a memory cell that achieves the retention of data during power-off periods.
FIG. 1
is a drawing showing an example of the construction of a related-art ferroelectric memory. The circuit shown in
FIG. 1
is a portion relevant to the reading of a ferroelectric memory, and includes 2T2C-type (2-transistor-and-2-capacitor-type) memory cell
1
, a pre-sense amplifier
2
, a pre-sense amplifier
3
, a Vth generating circuit
4
, a minus voltage generating circuit
5
, and a sense amplifier
6
.
In actual construction, a plurality of memory cells
1
is arranged in a matrix form. For the sake of simplicity of illustration, however, only one cell is shown in FIG.
1
. In the memory cell
1
, a word line WL, a plate line PL, bit lines BL and BLX, access transistors N
1
and N
2
, and ferroelectric capacitors F
1
and F
2
are provided.
In the ferroelectric memory, a write operation is performed by applying a positive or negative voltage to the ferroelectric capacitors for polarization, and a read operation is performed by detecting the presence/absence of a reversed polarization current when a positive voltage is applied to the ferroelectric capacitors. In the write operation, the word line WL is placed in a selected state (HIGH), thereby turning on the access transistor N
1
. When a positive or negative voltage is applied between the bit line BL and the plate line PL, this voltage is applied to the ferroelectric capacitor F
1
, resulting in desired data being stored. When writing “0” data, the bit line BL is set to 0 V, and the plate line PL is set to a power supply voltage VDD. When writing “1” data, the bit line BL is set to the power supply voltage VDD, and the plate line PL is set to 0 V. By following the same procedure, the ferroelectric capacitor F
1
stores data that is inverse to the data stored in the ferroelectric capacitor F
2
. Since the polarization of the ferroelectric capacitors is retained even after the applied voltage is removed following the write operation, the stored data remains as nonvolatile data.
In a read operation, the word line WL is selectively activated to turn on the access transistor N
1
, and the plate line PL is set to the power supply voltage VDD. The bit line BL is maintained substantially at a ground potential GND by the pre-sense amplifier
2
, and a positive voltage is applied to the ferroelectric capacitor F
1
. When “0” is stored in the ferroelectric capacitor F
1
, the voltage applied to the ferroelectric capacitor F
1
has the same polarity as used in the write operation, thereby resulting in no reversal of polarization. In this case, comparatively small electric charge flows into the bit line BL. When “1” is stored in the ferroelectric capacitor F
1
, the voltage applied to the ferroelectric capacitor F
1
has a reversed polarity compared with the polarity used in the write operation, thereby resulting in the reversal of polarization. In this case, comparatively large electric charge flows into the bit line BL. The pre-sense amplifier
2
detects this current, and converts it into a voltage signal. By the same token, the pre-sense amplifier
3
detects a current from the ferroelectric capacitor F
2
, and converts it into a voltage signal. The sense amplifier
6
amplifies a difference of the output potentials of the pre-sense amplifiers
2
and
3
up to the level of the power supply voltages VDD and GND.
The pre-sense amplifier
2
includes switches S
1
and S
3
, a Pch-MOS transistor P
1
, and capacitors C
1
and C
3
. The pre-sense amplifier
3
includes switches S
2
and S
4
, a Pch-MOS transistor P
2
, and capacitors C
2
and C
4
. The sense amplifier
6
includes Pch-MOS transistors P
3
-P
7
, Nch-MOS transistors N
3
-N
7
, switches S
5
and S
6
, and an inverter I
1
.
FIG. 2
is a diagram showing signal waveforms for explaining the operation of the related-art circuit of FIG.
1
. In the following, a description will be given of the operation of the circuit of
FIG. 1
with reference to FIG.
2
.
Data “1” is stored in the ferroelectric capacitor F
1
, and data “0” is stored in the ferroelectric capacitor F
2
. In
FIG. 2
, the switches S
1
and
52
are ON (i.e., closed) up to timing T
1
, so that the bit lines BL and BLX are fixed to the ground potential GND. After timing T
1
, the switches S
1
and S
2
are OFF (i.e., open), so that the bit lines BL and BLX are released. The Vth generating circuit
4
generates a potential that is equal to Vth (MOS threshold value) when the sources (i.e., the bit lines BL and BLX) of the Pch-MOS transistors P
1
and P
2
are at the ground potential GND. This potential is lower than GND.
The minus voltage generating circuit
5
generates a negative potential VMINUS. The negative potential VMINUS is −3 V, for example. The switches S
3
and S
4
are ON until timing T
1
, thereby setting the drains (i.e., nodes MINUS and MINUSX) of the Pch-MOS transistors P
1
and P
2
to the negative potential VMINUS. After timing T
1
, the switches S
3
and S
4
are OFF, so that the nodes MINUS and MINUSX are released. From timing T
1
to timing T
2
, the potential of the nodes MINUS and MINUSX is maintained at the negative potential VMINUS by means of the capacitors C
1
and C
2
.
At timing T
2
, the word line WL and the plate line PL are changed to VDD (e.g., 3 V). The access transistors N
1
and N
2
are turned on, and a positive voltage is applied to the ferroelectric capacitors F
1
and F
2
. Since the ferroelectric capacitor F
1
with stored data “1” receives a voltage having an opposite polarity compared with the polarity used in the write operation, a large amount of reversed electric charge flows into the bit line BL due to the reversal of polarization. In response, the potential of the bit line BL tries to rise. Since Vth is being applied to the gate of the Pch-MOS transistor P
1
, even a slight increase in the potential of the bit line BL causes the Pch-MOS transistor P
1
to turn on. Because of this, electric charge equal to the reversed electric charge flows from the bit line BL to the node MINUS, maintaining the potential of the bit line BL close to GND. In response to the influx of reversed electric charge, the potential of the node MINUS that was held steady by the capacitor C
1
rises significantly, as shown in FIG.
2
.
The voltage applied to the ferroelectric capacitor F
2
with stored data “0”, on the other hand, has the same polarity as used in write operation, resulting in no reversal of polarization. In this case, comparatively small electric charge flows into the bit line BLX. In response, the potential of the bit line BLX tries to rise. Since Vth is being applied to the gate of the Pch-MOS transistor P
2
, even a slight increase in the potential of the bit line BLX causes the Pch-MOS transistor P
2
to turn on. Because of this, electric charge flows from the bit line BLX to the node MINUSX, maintaining the potential of the bit line BLX close to GND. With the inflow of electric charge, the potential of the node MINUSX that was held steady by the capacitor C
2
rises as shown in FIG.
2
. Since the stored data is “0”, the rise of the potential of the node MINUSX is smaller than the rise of the potential of the node MINUS.
The switches S
5
and S
6
of the sense amplifier
6
are ON until timing T
1
, so that respective terminals OUT and OUTX of the capacitors C
3
and C
4
are fixed to GND until

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