Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-03-19
2004-12-14
Nguyen, Cuong (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S002000
Reexamination Certificate
active
06831316
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor memory device and a manufacturing method thereof.
BACKGROUND ART
Heretofore, demand for dynamic random access memories (DRAM) that has attained improvement for integration at a rate of four times per three year, has been increased more and more along with an explosive increase in the sales sum of personal computers in recent years. Already, mass production for 16 Mbits has passed the peak and development has been progressed at present for the mass production of 64 Mbits using a size of 0.2 &mgr;m or less as the micro-fabrication in the next generation.
The memory cell for DRAM from 16 Kb to those put into products at present is constituted with a transistor
50
as a switch and a capacitor
51
for accumulating storage charges. Such a memory cell is referred to as 1 transistor cell. In the memory cell, the signal voltage read to data line BL is determined depending on the ratio of the capacitance Cs to the capacitor voltage
51
and the parasitic capacitance Cd of the data line BL. Further, since the signal voltage of the memory cell is charged to the voltage for the data line by reading the information, it is destructive reading. Accordingly, the memory cell of this type requires a refreshing operation of rewriting the data. WL in the figure shows a word line.
One of the greatest-subjects in the memory cell is insurance of necessary and sufficient capacitance Cs of the capacitor with two view points of the signal voltage of the memory cell and the durability to the soft errors. In order to solve the subject, the memory cell is constituted as a three dimensional structure and the height for the capacitor has been increased more and more along with micro-miniaturization in order to ensure necessary and sufficient accumulation capacitance.
FIG. 2
shows an example of such a memory cell.
FIG. 2
shows a cross section for a portion of a memory array
60
and a peripheral circuit
61
. As described above, the height of the memory cell is increased for ensuring the capacitance thereof. In the example shown in
FIG. 2
, the capacitor
63
is mounted on a semiconductor substrate
77
disposed with a switching transistor
50
. The capacitor has a lower electrode
73
, an insulating layer
74
, and an upper electrode
75
. Since the capacitor is mounted on the semiconductor substrate, the height inevitably increases in order to ensure a desired capacitance for the capacitor. An example of such a memory cell is seen, for example, in
FIG. 1
of 1999, IEDM, pp 45-48.
However, increase for the height of the capacitor results in large height difference between the memory array
60
and the peripheral circuit
61
. This remarkably reduces the margin for various designs to the process including lithography. This directly leads to the increase of the manufacturing cost. It is inevitable that the problem will become severer in DRAM after 256 Mbits. In view of the background described above, it has been highly expected for a memory cell not requiring capacitor instead of the existent 1 transistor cell. As described above, it is anticipated a considerable difficulty for the attainment of DRAM after 256 Mbits of memory capacitance with the existent 1 transistor cell in view of a physical reason because of the increasing height of the capacitor.
Further, while an example of using a device that utilizes a multistable current state to a memory cell has also been reported, it has not yet been put to practical use at present. Such an example is described, for example, in U.S. Pat. Nos. 5,745,407 and 5,535,156.
The invention of the present application intends to drastically turn such current background.
DISCLOSURE OF INVENTION
In order to solve such problems, the invention of the present application provides a semiconductor memory device using a bistable diode not requiring a capacitor as a constituent element of the memory cell instead of the existent 1 transistor cell, as well as a manufacturing method thereof.
According to the invention of the present application, the cell area in semiconductor memory device is extremely small to enable high integration degree. Further, according to the invention of the present application, it can provide a semiconductor memory device requiring no refreshing and suitable to embedding with logics, as well as a manufacturing method thereof. More specifically, the invention of the present application can provide a random access memory (RAM) with extremely small memory cell area and capable of attaining high integration degree.
At first, for easy understanding, a basic concept of the invention of the present application is to be explained with reference to the drawings.
A bistable diode that can be used in the invention of the present application is a negative resistance element having at least a high impedance state and a low impedance state.
A specific structure in a typical example of a bistable diode that can be used in the invention of the present application has a basic structure as shown in FIG.
3
A. That is, the basic structure thereof comprises a multi-layered structure of a conductive layer (
1
)/insulating layer (
2
)
-type semiconductor layer (
3
)/p-type semiconductor layer (
4
). Substantially the same discussion can be applied also to a structure in which the order of layering is replaced between the n-type semiconductor (
3
) and the p-type semiconductor (
4
) excepting that the polarity is inverted. Typical examples of the n-type semiconductor layer (
3
) and the p-type semiconductor (
4
) are n-type silicon layer and p-type silicon layer, respectively. Accordingly, the n-type semiconductor layer (
3
) and the p-type semiconductor layer (
4
) are to be explained with silicon layers respectively. Further, the insulating layer can be constituted with plural insulating layers. This example is to be described later.
Now, in the structure shown in FIG.
3
(
a
), a positive bias is applied to the p-type silicon
3
. At the initial stage, an n-type silicon band is bent at the boundary of the insulating layer (
2
)
-type silicon layer (
3
). However, since holes are not accumulated at the boundary thereof in this case, a depletion layer
5
is formed on the surface of semiconductor crystals. FIG.
3
(
b
) is a band-structural view showing the state. The state in FIG.
3
(
b
) shows a so-called deep depression state. As a result, most of the application voltage is applied to the surface depletion layer formed in the boundary of the insulator (
2
)
-type silicon (
3
). Accordingly, since the voltage applied on the insulating layer (
2
) is weak, movement of the carriers by way of the insulating layer, for example, tunneling effect is inhibited. As a result, the memory cell is in a high impedance state. Reference numeral for each of the layers in FIG.
3
(
b
) corresponds to the structure shown in FIG.
3
(
a
). In the drawing, a small tunnel current
6
is shown by an arrow. Further, the state of the applied voltage to the insulating layer (
2
), so-called a tunnel film is depicted by reference numeral
9
. The movement of carriers by way of the insulating layer is to be explained by means of movement by a so-called tunneling effect.
Further, when the voltage applied to the p-type silicon is increased, hole current from a PN-junction
7
formed in the inside of the substrate increases to form an inversion layer
8
at the boundary of the insulator (
2
)
-type silicon (
3
). Accordingly, most of the application voltage is applied to the insulating layer (
2
). As a result, tunneling of electrons from the conductor (
1
) is enabled and since electrons injected from the conductor (
1
) neutralize donors of the n-type silicon layer (
3
), the barrier for the hole injection is further lowered and the current is further increased. Thus, the low impedance state of the memory cell is attained.
FIG. 3C
shows a band structural view in this state. The reference numerals for each of the layers in FIG.
3
(
c
) correspond to the structure in FIG.
3
(
a
). In the figure, a large tunnel current
6
is dep
Kachi Tsuyoshi
Kimura Shin'ichiro
Matsuoka Hideyuki
Sakata Takeshi
Sekiguchi Tomonori
Hitachi , Ltd.
Miles & Stockbridge P.C.
Nguyen Cuong
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