Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2003-08-07
2004-11-30
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S475000, C438S905000
Reexamination Certificate
active
06825124
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating semiconductor devices, and more particularly, to a method of forming a metal line in the semiconductor device which can minimize carbon loss in a low dielectric interlayer insulating film by implementing a hydrogen reactive cleaning process at low temperature and remove residua generated in a reduction reaction of a copper oxide film by in-situ implementing an annealing process within a chamber in which the hydrogen reactive cleaning process is implemented, whereby an interfacial characteristic of the low dielectric interlay insulating film is improved.
2. Background of the Related Art
As micro-process, a rapid operating speed and a high reliability are required, copper (Cu) is used as a metal line of the semiconductor device. In general, the copper line is formed using a dual damascene pattern by means of an electroplating method. After the copper film is formed by the electroplating method, an annealing process is implemented at a given temperature before a chemical mechanical polishing (CMP) process for the purpose of property stabilization.
Meanwhile, a physical method using sputter etch has been usually used in a cleaning process for a contact that opens a lower copper line. Due to this, there is a problem that Cu redeposition within the contact occurs. However, as a low dielectric film that is not dense is used as an interlay insulating film for the purpose of a high speed of the device, there is a need for a new technology for the cleaning. Research has recently been made on a reactive cleaning process using hydrogen reduction. However, the reactive cleaning process using hydrogen reduction has a problem that it causes surface damage in the low dielectric interlay insulating film containing carbon to degrade the dielectric characteristic of the interlay insulating film. In other words, as a reduction reaction of the copper oxide film on the surface of the copper film being the lower line, i.e., a Cu—O+H
+
→Cu+OH (or H
2
O) reaction occurs, residua such as OH radicals or H
2
O are created. Also, as SiOC+H
+
→Si—O+CH
4
reaction occurs at the sidewall of a contact hole formed within the interlay insulating film, carbon loss is caused. The low dielectric interlay insulating film of such carbon series is damaged by hydrogen. It was known that this phenomenon is severe when the processing temperature of the reactive cleaning process is high. Therefore, this problem must be solved from the viewpoint of reliability of the semiconductor.
SUMMARY OF THE INVENTION
Accordingly, the present invention is contrived to substantially obviate one or more problems due to limitations and disadvantages of the related art, and an object of the present invention is to provide a method of forming a metal line in a semiconductor device which can minimize carbon loss in a low dielectric interlayer insulating film by implementing a hydrogen reactive cleaning process at low temperature and remove residua generated in a reduction reaction of a copper oxide film by in-situ implementing the annealing process within a chamber in which the hydrogen reactive cleaning process is implemented, whereby an interfacial characteristic of the low dielectric interlay insulating film is improved.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a method of forming a metal line in a semiconductor device according to the present invention is characterized in that it comprises the steps of forming an interlay insulating film on a semiconductor substrate in which a lower line is formed, patterning the interlay insulating film to form an aperture unit for forming an upper line connected to the lower line, cooling the semiconductor substrate in which the aperture unit is formed at a given temperature, implementing a cleaning process using a hydrogen reduction reaction in order to remove polymer formed on the sidewall of the aperture unit and a metal oxide film formed on the lower line, implementing an annealing process in-situ within a chamber in which the cleaning process is implemented, and burying the aperture unit with a conductive material to form an upper line.
The aperture unit may be a contact hole, a trench, a single damascene pattern, or a dual damascene pattern consisting of a via hole and a trench.
It is preferred that the cleaning process is implemented using H
2
gas and Ar gas or H
2
gas, Ar gas and N
2
gas at a low temperature of about 25° C.~50° C. The cleaning process may be implemented by implanting H
2
gas of 2~15 sccm and Ar gas of 4~30 sccm at a pressure of 1.5~3 mT, a source power of 500~750 W and a bias power of 0~100 W, or implanting H
2
gas of 2~15 sccm, N
2
gas of 2~15 sccm and Ar gas of 4~30 sccm at a pressure of 1.5~3 mT, a source power of 500~750 W and a bias power of 0~100 W.
The annealing process is implemented in two steps, wherein the first step is implemented at a relatively low temperature of blow 100° C.~150° C. in order to mitigate stress and detach the residua such as OH radicals or H
2
O absorbed on the sidewall of the aperture unit, and the second step is implemented at a relatively high temperature of about 300° C.~400° C. in order to accomplish densification of the interlay insulating film and the lower line.
The interlay insulating film may be an insulating film of SiOC series having a low dielectric constant.
The lower line may include a copper film.
In another aspect of the present invention, it is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
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patent: 5935762 (1999-08-01), Dai et al.
patent: 5997757 (1999-12-01), Nagayama et al.
patent: 6057247 (2000-05-01), Imai et al.
patent: 6126806 (2000-10-01), Uzoh
patent: 6235406 (2001-05-01), Uzoh
patent: 6355571 (2002-03-01), Huang et al.
patent: 6380096 (2002-04-01), Hung et al.
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
Nhu David
LandOfFree
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