Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-06-23
2004-10-26
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S506000, C257S019000
Reexamination Certificate
active
06809380
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) of an SOI (Silicon-On-Insulator) structure.
The problem in this type of traditional semiconductor device is described in the document below.
C. I. Huang et al.,
LOCOS
-
Induced Stress Effects on Thin
-
Film SOI Devices
, IEEE ELECTRON DEVICE LETTERS, Vol. 44, No. 4, pp. 646-650, April 1997.
FIGS. 6A and 6B
depict semiconductor devices having a MOSFET of a traditional SOI structure.
FIG. 6A
depicts a partially-depleted (PD) device, and
FIG. 6B
depicts a fully-depleted (FD) device. As shown in
FIGS. 6A and 6B
, these semiconductor devices have a semiconductor substrate
21
, a buried oxide film (BOX film)
22
formed on the substrate
21
, and an SOI film
25
formed thereon. A source and a drain
31
and a channel
27
of the MOSFET are formed on the SOI film
25
, a gate insulating film
28
is formed thereon, and a gate electrode
29
is formed thereon. A sidewall
30
is formed on both sides of the gate electrode
29
. In addition, this MOSFET is isolated from the other adjacent devices such as similar MOSFETs by a device isolation film
26
.
The difference in the structure between the partially-depleted (PD) device and the fully-depleted (FD) device is the thickness tSOI of the SOI film
25
. Generally, it is about 100 to 200 nm in the partially-depleted device, while a thin SOI film having a thickness of 50 nm or below is used in the fully-depleted device.
Because of the structural characteristics, the SOI (Silicon-On-Insulator) MOSFET has advantages such as small parasitic capacitance, no latchup, a low soft error rate, and relatively easy device isolation, attracting a keen interest in the probability of applications to a high-speed, low-power consumption LSI. Particularly, in the fully-depleted SOI device shown in
FIG. 6B
, a depleted layer formed under the gate reaches the buried oxide film
22
below the SOI film
25
. Thus, the capacitance in the depleted layer becomes small, and a substhreshold factor (S value) is reduced to nearly a desired value. On this account, the MOSFET has the advantage that the threshold voltage (Vth) can be made smaller than that of a bulk device or the partially-depleted SOI device (
FIG. 6A
) when the same off leakage current is set.
SUMMARY OF THE INVENTION
However, the above-described document reports the result that the transconductance (gm) of the NMOSFET is more reduced in the
501
device than in the bulk device. This report is in the case of using LOCOS (Local Oxidation Of Silicon) for device isolation; the transconductance is greatly reduced as the oxide film is thicker. Inversely, in the PMOSFET, the transconductance is increased as the oxide film is thicker. This is because the oxide film (SiO2 film) in the device isolation region is expanded in volume to apply compressive stress to the SOI film. A reduction in the current value caused by the stress is nearly 40% at the maximum, and the merits of the SOI device are cancelled. Therefore, it is important to reduce the stress.
The paper reports that the stress in the device isolation region affects the transconductance to be reduced. However, the inventors observe the phenomenon that current is more reduced in the NMOSFET than in the bulk device whereas it is increased in the PMOSFET even in the case where the device isolation film is formed very thin to sufficiently reduce the stress applied from the device isolation region. The cause is considered to be the influence of the stress generated by the difference between the thermal expansion coefficients of Si and SiO
2
upon carrier mobility, which is considered to have small influence in the paper.
FIG. 7
schematically depicts the stress generated in a multilayer film. The thermal expansion coefficient of Si is 2.5×10
−6
/° C., and that of SiO
2
is 5×10
−7
/° C. When annealed at temperature that silicon oxide becomes viscous (at a temperature of around 1000° C.) in the fabrication process of the semiconductor device, Si and SiO
2
are in a flat state. The Si film is significantly contracted by the difference in thermal expansion coefficient in temperature drop from that temperature. Consequently, the multilayer film is warped downward as shown in the drawing, and thus the compressive stress is generated on the top side of the Si film.
The stress generated by the difference between the thermal expansion coefficients becomes greater as the ratio of the SOI film thickness to the BOX film thickness (the SOI film thickness/the BOX film thickness) is greater. On this account, the fully-depleted SOI device having a thin SOI layer tends to be affected greatly. When the BOX film is formed thinner, the influence of the stress generated by the difference between the thermal expansion coefficients is reduced. However, advantages such as low parasitic capacitance being the merit of the SOI device and a small S value in the fully-depleted SOI device are cancelled.
Then, the object of the invention is to provide a semiconductor device having a MOSFET of an SOI structure with such excellent characteristics as the semiconductor device is hardly affected by the stress generated by the difference between the thermal expansion coefficients of the BOX film and the SOI film and has low parasitic capacitance and a small S value.
A semiconductor device of the invention is characterized by having:
a lower buried oxide film disposed on a semiconductor substrate;
a stress-relief film disposed on the lower buried oxide film;
an upper buried oxide film disposed on the stress-relief film; and
an SOI film disposed on the upper buried oxide film,
wherein the SOI film is formed with a MOSFET having a source, a drain, and a channel, and
a thermal expansion coefficient of the stress-relief film is greater than a thermal expansion coefficient of the upper buried oxide film.
The stress-relief film desirably has the thermal expansion coefficient nearly equal to or greater than the thermal expansion coefficient of the SOI film.
For example, the stress-relief film may be formed of a silicon film. Alternatively, it may be formed of a composite film laminating a first silicon film, a germanium film disposed thereon, and a second silicon film disposed thereon.
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Cheng-Liang Huang et al., “LOCOS-Induced Stress Effects on Thin-Film SOI Devices”, IEEE Electron Device Letters, vol. 44, No. 4, Apr. 1997, pp. 646-650.
Oki Electric Industry Co. Ltd.
Soward Ida M.
Wenderoth , Lind & Ponack, L.L.P.
Zarabian Amir
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