Sputtered insulating layer for wordline stacks

Details Sputtered insulating layer for wordline stacks Sputtered insulating layer for wordline stacks

2003-08-14

2004-11-09

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S758000

Reexamination Certificate

active

06815372

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of semiconductor device fabrication. In one aspect, the invention relates to the manufacture of a wordline stack while in another aspect, the invention relates to forming an insulating layer on the top surface of the stack. In yet another aspect, the invention relates to depositing the insulating layer on the wordline stack through the use of sputtering technology.
BACKGROUND OF THE INVENTION
Dynamic random access memory (DRAM) devices comprise, among other things, a large plurality of wordline stacks, also known as gate electrode stacks. The function of these stacks is to store a charge and when used in combination with a bit or digit line, provide an “address” for a discrete memory cell. The typical wordline stack is a layered composite of various materials, the top layer of which is typically a silicate glass, e.g., borophosphosilicate glass (BPSG).
The preparation of a DRAM device involves one or more heat annealing steps in which the temperature is such that the dopants, e.g., boron, phosphorus, arsenic, etc., of a doped material, e.g., BPSG, will migrate (or out-gas) from the doped material into the environment (i.e., into the chamber in which the heat annealing step is conducted) and into one or more adjacent layers or other components, e.g., the substrate, of the device. Since the purpose of a dopant is to enhance the conductivity of a material, migration of a dopant into a dielectric material will decrease the insulating properties of that material. If enough dopant migrates into a dielectric material, then the insulating properties of the material will be reduced to the point that a short circuit can develop between the conductive layers separated by the dielectric layer. This, of course, means that a wordline stack can lose its charge inadvertently and this, in turn, can result in a malfunction of the memory device.
To address this problem, a relatively thick, e.g., 150-300 angstroms, layer of an insulating material (also a dielectric and also known as a liner) is usually deposited adjacent to a layer of doped material. Tetraethylorthosilicate (TEOS) is a commonly used liner for this purpose. Achieving a relatively thick layer of this insulating material using conventional chemical vapor deposition (CVD) techniques is not difficult for top-level stack surfaces, but it can be problematic for the surfaces between two stacks. If the aspect ratio, i.e., the height of the stacks (the height of all of the stacks is, for all intent and purpose, essentially the same at the time a blanketing layer of insulating material is deposited) over the distance between the stacks, is relatively low, e.g., less than 3, then conventional CVD techniques will deposit a layer of insulating material of substantially the same thickness between two stacks as is deposited on the top of the stacks. However, as this aspect ratio increases, i.e., the distance between the stacks narrows, the thickness of the insulating layer deposited by conventional CVD between two stacks decreases relative to the thickness of the insulating surface deposited on the top layer of the stacks. At some point, insufficient insulating material is deposited between the two stacks to provide an effective block against the migration of dopants from a material overlying the insulating layer to a material underlying the insulating layer.
As the density of wordline stacks increase on a substrate, the space between individual stacks will inevitably decrease. As this space decreases, the need for cleaner production methods increases, including the need to block the migration of dopants from a doped material to a dielectric material during the heat annealing steps of the memory device. This increases the need for adequate deposition of liners between wordline stacks during the preparation of semiconductor memory devices and other integrated circuits.
SUMMARY OF THE INVENTION
According to this invention, a liner that is an effective block against the migration of a dopant from a doped material to a dielectric material is positioned between the two materials by sputtering. In one embodiment of this invention, an insulating material is deposited onto a gate dielectric surface separating two wordline stacks, the method comprising the steps of:
A. Forming at least two adjacent wordline stacks over a common gate dielectric, the stacks spaced apart from one another thereby forming an open surface on the gate dielectric between the stacks; and
B. Depositing by sputtering the insulating material onto the open surface of the gate dielectric separating the two wordline stacks.
In another embodiment of this invention, an insulating material is deposited onto a gate dielectric surface separating two wordline stacks, each wordline stack having a top surface, the insulating material deposited as a layer onto the dielectric surface at a thickness that is substantially the same as the thickness of the insulating layer that is deposited as a layer onto the top of the stacks, the method comprising the steps of:
A. Forming at least two adjacent wordline stacks over a common gate dielectric, the stacks spaced apart from one another thereby forming an open surface on the gate dielectric between the stacks; and
B. Depositing by sputtering the insulating material as a layer onto the top of the two stacks and the open surface of the gate dielectric separating the two wordline stacks.
In still another embodiment of this invention, an insulating material is deposited onto a gate dielectric surface separating two wordline stacks, each wordline stack having a top surface and at least one side wall, the insulating material deposited as a layer onto the dielectric surface (i) at a thickness that is substantially the same as the thickness of the insulating layer that is deposited as a layer onto the top of the stacks, and (ii) without any substantial deposition of the insulating material onto the side walls of the stacks, the method comprising the steps of:
A. Forming at least two adjacent wordline stacks over a common gate dielectric, the stacks spaced apart from one another thereby forming an open surface on the gate dielectric between the stacks; and
B. Depositing by sputtering the insulating layer onto the top of the two stacks and the open surface of the gate dielectric separating the two wordline stacks without any substantial deposition of the insulating material onto the side walls of the stacks.


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