Vertically structured power semiconductor component

Details Vertically structured power semiconductor component Vertically structured power semiconductor component

2001-04-19

2004-12-14

Tran, Minhloan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S355000, C257S288000

Reexamination Certificate

active

06831327

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a vertically structured power semiconductor component having a semiconductor body of a first conductivity type, a first main surface and a second main surface opposite the first main surface. A body zone of a second conductivity type, opposite of the first conductivity type, is introduced into the first main surface. A zone of the first conductivity type, is provided in the body zone. A first electrode makes contact with the zone of the first conductivity type and with the body zone. A second electrode is provided on the second main surface, and a gate electrode, is disposed above the body zone and is separated from the latter by an insulating layer.
In semiconductor power components, it is desirable to carry the largest possible current through the smallest possible area. In order to optimize the channel width/channel length or area ratio, power semiconductor components are therefore built from a large number of cells connected in parallel, in each of which the current path runs in the vertical direction, i.e. from one main surface of the semiconductor body to its other main surface. In this way, all of the semiconductor material placed under the actual cell in question, i.e. as far as the back terminal placed on the other main surface, is used as an active volume.
It will be assumed below that the power semiconductor component is an n-channel power MOS field-effect transistor, in which the source and gate terminals are located on one main surface of the semiconductor body, the chip top, and the drain terminal is located on the other main surface of the semiconductor body, the chip bottom.
The ideas below, however, can also be applied readily to other power semiconductor components, for example insulated gate bipolar transistors (IGBT) etc.
A power semiconductor component receives the voltage applied to it through mutual depletion of neighboring p- and n-conductive regions by mobile charge carriers, so as to create a space charge zone. In an n-channel power MOS field-effect transistor, spatially fixed charges created in a p-conductive well hence find their “mirror charges” primarily in a vertically adjacent n-conductive layer, which is normally produced by epitaxy. The maximum of the electric field always occurs at the pn junction between the p-conductive well and the semiconductor body. Electrical breakdown is reached when the electric field exceeds a material-specific critical field strength E
c
: this is because multiplication effects then lead to the creation of free charge carrier pairs, so that the blocking-state current suddenly increases greatly. But since, as is know, charges are the sources of any electric field, this critical field strength E
o
can be assigned an equivalent critical breakdown surface charge Q
c
according to the first Maxwell equation. For silicon, for example, E
c
=2.0 . . . 3.0×10
5
V/cm and Q
c
1.3−1.9×10
12
charge carriers cm
−2
. Since each charge carrier has the charge of e (electronic charge=1.6×10
−19
As), Q
c
can take values from 2.08−3.04×10
−7
As.cm
−2
. The exact value of Q
c
depends in this case on the level of the doping.
The voltage reduction in a power semiconductor component, which takes place in the cell array in the lower-lying volume of the semiconductor body, must also be defined toward its edge, a profile in the horizontal direction being desirable in this case. Elaborate surface-positioned equipotential structures are commonly employed in order to achieve this.
The breakdown response of power semiconductor components can be evaluated in static measurements. An “avalanche test”, however, in which the switching response is also tested in addition to the actual breakdown, is much more meaningful. In this case, different regions of the safe operating area (SOA) are run through during a test. The purpose of such measurements is to simulate the “worst case” for user applications. In order to comply with the various requirements, a power semiconductor component must, in particular, meet the below listed criteria.
First, during electrical breakdown, an impressed high current due to charge-carrier multiplication flows from the external circuit. In order to prevent destruction of the power semiconductor component, however, excessively high current densities should be avoided. Therefore, the breakdown current must be distributed as uniformly as possible across the semiconductor body, or chip. But this criterion can only be met if the actual cell array carries the major part of the breakdown current. The reason is that if the power semiconductor component breaks down in its edge structure at lower voltages than the cell array, this usually causes irreversible thermal damage to the semiconductor body, or chip. The difference in blocking voltage between the edge region and the cell array must hence be made large enough so that fabrication tolerances do not shift the breakdown towards the edge region. In general, it may hence be stated that the voltage strength of the edge region must be higher than that of the cell array.
Second, owing to fabrication tolerances, the electrical breakdown never takes place homogeneously across the entire semiconductor body, or chip. Instead, the breakdown is defined by the “weakest” cell. So in order to achieve homogenization across the cell array, the voltage at such weakest cells must become higher as the breakdown current grows, since other cells will then also enter breakdown and in turn “shift” their voltage. This distributes the “avalanche current” uniformly across the cell array. In standard power semiconductor components, the heating of the semiconductor material is normally sufficient to ensure a positive differential current/voltage response. Dynamic doping effects in which, for example, the effects of mobile charge carriers from the breakdown current are to be added to the background doping, can also facilitate such a characteristic.
In any case, the power semiconductor component should have a positive differential current/voltage response in the event of electrical breakdown.
Third, in MOS transistors, as is known, each cell contains a “three-layer system” which contains a source zone, a body zone and a drain zone, and can act as a parasitic bipolar transistor for holes created in breakdown. The base of this bipolar transistor is in this case formed by the p-conductive well. If this base then experiences a voltage drop in the region of about 0.7 V as a result of the hole current, then the bipolar transistor is switched on and draws more and more current without any further way of controlling it, until the power semiconductor component is finally destroyed. This behavior is ultimately due to the negative temperature/resistance curve for bipolar transistors. However, such effects can be counteracted by configuration precautions. One very effective way is to avoid crossover currents at the surface, i.e. to place the electrical breakdown as deeply and centrally as possible below each cell. In other words, parasitic bipolar effects should be avoided wherever possible.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a vertically structured power semiconductor component that overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which a simple configuration is used to ensure that any electrical breakdown reliably occurs in the cell array.
With the foregoing and other objects in view there is provided, in accordance with the invention, a vertically structured power semiconductor component. The power semiconductor components contains a semiconductor body of a first conductivity type that has a first main surface and a second main surface opposite the first main surface. A body zone of a second conductivity type opposite of the first conductivity type is introduced into the first main surface. A zone of the first conductivity type is disposed in the body zone. A first elec

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