Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-25
2004-08-31
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S324000, C257S315000, C257S637000, C257S638000, C257S314000, C438S263000, C438S464000, C438S594000
Reexamination Certificate
active
06784484
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an insulating barrier provided for tunnelling electrons from a first conductive region to a second conductive region according to the preamble of the first claim.
BACKGROUND OF THE INVENTION
Such an insulating barrier is for example used in a non-volatile memory (NVM) device, in which the first conductive region is for example a floating gate. In such memory devices it is desired that charge which is put on the floating gate can remain there for a long period of time, (for example 10 years) which period is referred to as the retention time. On the other hand it is desired that the charge can be removed from the floating gate by tunnelling in a very short time (for example in the order of milli- or microseconds), which time is referred to as the erase time, or transferred to the floating gate by tunnelling in an even shorter time (for example in the order of microseconds), which time is referred to as the write time. In order to achieve such short write/erase times, a suitable tunnelling voltage is applied over the insulating barrier, which is above the maximum read-disturbance voltage (i.e. the maximum voltage at which no significant undesired tunnelling occurs). This suitable tunnelling voltage is strongly dependent on the dielectric material in which the barrier is constructed and by its thickness.
Conventionally, the insulating barrier is constructed as a single layer of a dielectric material. The material and the thickness of the layer are chosen in function of a desired compromise between, on the one hand, obtaining a maximum read disturbance voltage as high as possible and, on the other hand, making it possible to write or erase the floating gate by applying a voltage as low as possible. Such a single-layer insulating barrier has an energy band diagram as shown in
FIGS. 2 and 3
,
FIG. 2
showing the diagram in absence of a voltage applied over the barrier and
FIG. 3
showing the diagram upon applying the tunnelling voltage.
FIG. 3
clearly shows that the tunnelling voltage of the single-layer insulating barrier is undesirably high.
An insulating barrier which requires a lower voltage for tunnelling is for example known from U.S. Pat. No. 6,121,654. This document discloses a non-volatile memory device having an insulating barrier which is constructed as a three-layered structure. A first layer and a third layer of the insulating barrier are constructed in a low-barrier material and a second layer which is interposed between the first and third layers is constructed in a high-barrier material. As a result, the insulating barrier has a stepped energy band diagram with a lower level over the first and third layers and a higher level over the second layer (see FIGS.
5
and
6
). The low- and high-barrier materials have substantially the same dielectric constant. As a consequence, the energy band diagram of the barrier during tunnelling has substantially the same inclination over the three layers. By applying the low-barrier material between the first conductive region, i.e. the floating gate, and the high-barrier material of the second layer, it is achieved that the peak of the energy band diagram during tunnelling is reduced with respect to that of a single-layer insulating barrier. As a result, the tunnelling voltage of the insulating barrier is reduced with respect to that of the single-layer insulating barrier.
However, the insulating barrier described in U.S. Pat. No. 6,121,654 has the disadvantage that such a barrier cannot easily be constructed, as there are only few suitable material combinations, and that all of these combinations have practical problems. U.S. Pat. No. 6,121,654 describes only one possible combination, namely Si
3
N
4
as low-barrier material and AlN as high-barrier material. Depositing an AlN-layer is mostly done by epitaxial growth, wherein the ordered structure of the underlying layer is used as a template to assemble a high quality AlN layer. However, Si
3
N
4
does not have the required ordered structure and therefore the structure of the AlN layer that is deposited on a Si
3
N
4
layer will have defects that can compromise the long term data retention. Hence AlN is not a suitable material for constructing such an insulating barrier.
Aim of the Invention
It is an aim of the invention to provide an insulating barrier which can more easily be constructed and with which the tunnelling voltage can be reduced.
SUMMARY OF THE INVENTION
The insulating barrier according to one aspect of the invention comprises a first portion contacting the first region and a second portion contacting the first portion and extending towards the second region. The first portion is substantially thinner than the second portion. The first portion is constructed in a first dielectric and the second portion in a second dielectric which differs from and has a higher dielectric constant than the first dielectric. Due to the higher dielectric constant of the second portion, the first portion will have a larger voltage drop than the second portion when a voltage is applied over the insulating barrier. In other words, the electric field over the first portion will be stronger than the electric field over the second portion. As a result, the energy band diagram over the first portion has a stronger voltage dependence than the energy band diagram over the second portion, i.e. the energy band diagram upon applying a suitable voltage for tunnelling will show a steeper inclination over the first portion than over the second portion. In this way, less tunnelling voltage is required with respect to the single-layer insulating barrier of the prior art in order to reduce the energy barrier during tunnelling by the same amount. Furthermore, as the first portion is substantially thinner than the second portion, the profile during tunnelling comprises a larger part with the more shallow inclination, which implies that the tunnelling voltage can be reduced by a substantial amount with respect to the single-layer insulating barrier.
Suitable material combinations for the insulating barrier of the invention are for example SiO
2
or Si
3
N
4
for the first portion and Al
2
O
3
, HfO
2
or ZrO
2
for the second portion. The second portion can for example be deposited by a technique such as atomic layer chemical vapour deposition (ALCVD), which can easily be achieved. Furthermore, Al
2
O
3
, HfO
2
and ZrO
2
are high-barrier materials which are currently considered for use in standard silicon semiconductor technology, for example in the standard CMOS transistor process, in contrary to the AlN which is used in the barrier of U.S. Pat. No. 6,121,654 and is not a commonly used or considered material in silicon technology. As a result, the insulating barrier of the invention can be constructed more easily, as the use of additional materials which are not already used in the normal transistor manufacturing process can be avoided. Of course, any other material combinations which are deemed suitable to the person skilled in the art may also be used in the insulating barrier of the invention.
The first and second dielectrics in which the first and second portions of the insulating barrier according to the invention are constructed preferably each comprise a single dielectric material. However, the first and second dielectrics may each also comprise a plurality of suitable dielectric materials which are stacked on top of each other, as long as the average dielectric constant of the first portion is lower than the average dielectric constant of the second portion.
Preferably, the material and the thicknesses of the first and second portions are chosen such that, upon applying a voltage suitable for tunnelling over the insulating barrier, the voltage drop over the first portion is higher than the voltage drop over the second portion. This has the advantage that the largest part of the tunnelling voltage will be dropped over the first portion, which is substantially thinner than the second portion. As a result, the tunnelling voltage can be furth
Blomme Pieter
Govoreanu Bogdan
Rosmeulen Maarten
Flynn Nathan J.
Forde Remmon R.
Interuniversitair Micoroelektronica Centrum (IMEC, vzw)
McDonnell Boehnen & Hulbert & Berghoff LLP
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