Ferroelectric nonvolatile semiconductor memory

Details Ferroelectric nonvolatile semiconductor memory Ferroelectric nonvolatile semiconductor memory

2003-07-03

2004-11-16

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000

Reexamination Certificate

active

06819581

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a ferroelectric-type nonvolatile semiconductor memory (so-called FERAM).
BACKGROUND ART
In recent years, studies are actively made with regard to a ferroelectric-type nonvolatile semiconductor memory having a large capacity. A ferroelectric-type nonvolatile semiconductor memory (to be sometimes abbreviated as “nonvolatile memory” hereinafter) permits rapid access and is nonvolatile and small, and it consumes less electric power and has strength against an impact, so that it is expected to be used as a main storage device in various electronic machines and equipment having functions of file storage and resume, such as a portable computer, a cellular phone and a game machine, or as a recording medium for recording voices or images.
The above nonvolatile memory is a fast rewritable nonvolatile memory according to a method in which a change in an accumulated charge amount in a capacitor member having a ferroelectric layer is detected by utilizing fast polarization inversion and residual polarization of the ferroelectric layer, and the nonvolatile memory basically comprises the memory cell (capacitor member) and a transistor for selection (transistor for switching). The memory cell (capacitor member) comprises, for example, a lower electrode, an upper electrode and the ferroelectric layer interposed between these electrodes. Data is written into and read out from the above nonvolatile memory by using the P-E (V) hysteresis loop of the ferroelectric layer shown in FIG.
23
. That is, when an external electric field is applied to the ferroelectric layer and then removed, the ferroelectric layer exhibits residual polarization. When an external electric field in the plus direction is applied, the residual polarization of the ferroelectric layer comes to be +P
r
, and when an external electric field in the minus direction is applied, it comes to be −P
r
. When the residual polarization is in the state of +P
r
(see “D” in FIG.
23
), such a state represents “0”, and when the residual polarization is in the state of −P
r
(see “A” in FIG.
23
), such a state represents “1”.
For discriminating the state of “1” or “0”, an external electric field, for example, in the plus direction is applied to the ferroelectric layer, whereby the polarization of the ferroelectric layer comes into the state of “C” in FIG.
23
. In this case, when the data is “0”, the polarization state of the ferroelectric layer changes from the state of “D” to the state of “C”. When the data is “1”, the polarization state of the ferroelectric layer changes from the state of “A” to the state of “C” through the state of “B”. When the data is “0”, the polarization inversion does not take place in the ferroelectric layer. When the date is “1”, the polarization inversion takes place in the ferroelectric layer. As a result, there is caused a difference in the accumulated charge amount in the memory cell (capacitor member). The above accumulated charge is detected as a signal current by bringing, into an ON-state, the transistor for selection in a selected nonvolatile memory. When the external electric field is brought into 0 after data is read out, the polarization state of the ferroelectric layer comes into the state of “D” in
FIG. 23
both when the data is “0” and when it is “1”. That is, when the data is read out, the data “1” is once destroyed. When the data is “1”, therefore, the polarization is brought into the state of “A” through “D” and “E” by applying the external electric field in the minus direction, to re-write data “1”.
ABO
3
type ferroelectric oxides such as lead titanate zirconate [PZT, Pb(Zr,Ti)
3
] and lanthanum lead titanate zirconate [(Pb,La)(Zr,Ti)O
3
] have been mainly developed as a ferroelectric material for constituting the ferroelectric layer, and part of them has been put to practical use in a nonvolatile memory.
The structure and the operation of a currently mainstream nonvolatile memory are proposed by S. Sheffiled et al. in U.S. Pat. No. 4,873,664. The above nonvolatile memory comprises two nonvolatile memory cells as shown in a circuit diagram of FIG.
24
. In
FIG. 24
, each nonvolatile memory is surrounded by a dotted line. Each nonvolatile memory comprises, for example, transistors for selection TR
11
and TR
12
and memory cells (capacitor members) FC
11
and FC
12
.
Concerning two-digit or three-digit subscripts, for example, a subscript “11” is a subscript that should be shown as “1,1”, and for example, a subscript “111” is a subscript that should be shown as “1,1,1”. For simplified showing, the subscripts are shown as two-digit or three-digit subscripts. Further, a subscript “M” is used to show, for example, a plurality of memory cells or plate lines in the block, and a subscript “m” is used to show an individual, for example, of a plurality of the memory cells or the plate lines. A subscript “N” is used to show, for example, transistors for selection or memory units in the block, and a subscript “n” is used to show, for example, an individual of the transistors for selection or the memory units.
Complementary data is written into a pair of the memory cells, and the nonvolatile memory stores 1 bit. In
FIG. 24
, symbol “WL” stands for a word line, symbol “BL” stands for a bit line, and symbol “PL” stands for a plate line. When one nonvolatile memory is taken, the word line WL
1
is connected to a word line decoder/driver WD. The bit lines BL
1
and BL
2
are connected to a sense amplifier SA. Further, the plate line PL
1
is connected to a plate line decoder/driver PD.
When the stored data is read out from the thus-structured nonvolatile memory, the word line WL
1
is selected, and further, the plate line PL
1
is driven. In this case, the complementary data appears on a pair of the bit lines BL
1
and BL
2
as voltages (bit line potentials) from a pair of the memory cells (capacitor members) FC
11
and FC
12
through the transistors for selection TR
11
, and TR
12
. The voltages (bit line potentials) on the pair of the bit lines BL
1
and BL
2
are detected with the sense amplifier SA.
One nonvolatile memory occupies a region surrounded by the word line WL
1
and a pair of the bit lines BL
1
and BL
2
. If the word lines and the bit lines are arranged at a smallest pitch, therefore, the smallest area of one nonvolatile memory is 8F
2
when the minimum fabrication dimension is “F”. Therefore, the thus-structured nonvolatile memory has a smallest area of 8F
2
.
When it is attempted to increase the capacity of the above-structured nonvolatile memories, its realization can only rely on minuteness of fabrication dimension. Constitution of one nonvolatile memory requires two transistors for selection and two memory cells (capacitor members). Further, it is required to arrange the plate lines at the same pitch as that at which the word lines are arranged. It is therefore almost impossible to arrange the nonvolatile memories at the minimum pitch, and in reality, the area that one nonvolatile memory occupies comes to be much greater than 8F
2
.
Moreover, it is also required to arrange the word line decoders/drivers WD and the plate line decoders/drivers PD at a pitch equal to a pitch at which the nonvolatile memories are arranged. In other words, two decoders/drivers are required for selecting one low-address. It is therefore difficult to layout peripheral circuits, and the area that the peripheral circuits occupy comes to be large.
One means for decreasing an area of a nonvolatile memory is disclosed in JP-A-121032/1997. As
FIG. 25
shows a circuit diagram, the nonvolatile memory disclosed in the above Laid-open comprises a plurality of memory cells MC
1M
(for example, M=4) one end of each of which is connected to one end of one transistor for selection TR
1
in parallel, and a plurality of memory cells MC
2M
one end of each of which is connected to one end of one transistor for selection TR
2
in parallel. The other ends of the transistors for selection TR
1
and TR
2
are connected to bit line

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