Method for planarizing a copper interconnect structure

Details Method for planarizing a copper interconnect structure Method for planarizing a copper interconnect structure

2003-03-18

2004-08-31

Pert, Evan (Department: 2829)

Semiconductor device manufacturing: process

Chemical etching

C700S121000

Reexamination Certificate

active

06784107

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor substrate processing systems. More specifically, the present invention relates to a method for planarizing a copper interconnect structure in a semiconductor substrate processing system.
2. Description of the Related Art
In the semiconductor industry, much effort is spent in developing smaller integrated circuit (IC) devices with ever-increasing operating speed. Among of the factors affecting the operating speed of the IC devices are circuit density and a value of the dielectric constant of an inter-metal dielectric (IMD) layer in a wiring network of the IC device. To increase the circuit density, a dual damascene technique is used during fabrication of the IC devices, and, to increase the operating speed, the IMD layers are formed using materials having a dielectric constant less than 4 (i.e., less than a dielectric constant of silicon dioxide (SiO
2
)). Such materials are commonly referred to as low-K materials. The low-K materials comprise carbon-doped dielectrics, such as organic doped silicon glass (OSG), organic polymers (e.g., benzocyclobutene, parylene, polytetrafluoroethylene, polyether, polyimide), and the like.
The IC device comprises a plurality of wiring layers formed from conductive lines that are separated from each other and from a substrate (e.g., silicon (Si) wafer) by the IMD layers. The dual damascene technique includes forming an insulator layer (e.g., IMD layer) on the substrate. In an IMD layer, trenches and openings are etched to position the conductive lines and contact holes, or vias. Then, a barrier layer (e.g., layer comprising tantalum (Ta) and tantalum nitride (TaN) films) and a metal layer (e.g., copper (Cu) layer) are sequentially deposited upon the IMD layer to form a conductive interconnect structure. The barrier layer improves adhesion between the low-K IMD layer (e.g., OSG layer) and the copper, as well as impedes diffusion of copper and oxygen into the low-K material. The copper fills (metallizes) the trenches and openings in the IMD layer, thus forming conductive lines and vias, respectively. After metallization, the IMD layer should be planarized. During a planarization process, the excess metal and the underlying barrier layer are removed and conductive lines and vias are formed in the IMD layer. The conductive lines and vias are embedded in the IMD layer coplanar with an exposed surface of the layer such that the next wiring layer may be formed on top of the IMD layer.
In the prior art, such excess copper and the underlying barrier layer are removed from the surface of the IMD layer using chemical-mechanical polishing (CMP) process. During the CMP process, material above a feature such as a trench is removed at a higher rate than in other areas resulting in a concave cross-sectional pattern (or dishing) of the metallization. A depth of the concave pattern generally is in a range between 200 and 500 Angstroms. Compressive and rotational forces applied to a surface of the IMD layer during the CMP process may also cause erosion, as well as cracking and peeling, of the dielectric material in the IMD layer.
The thinned copper and barrier layers in the portion near the edge of the substrate are removed using an etchback process. However, the etchback process of the prior art can remove only very thin films of copper, e.g., films having a thickness of about 50 Å Angstroms. Such etchback process quickly self-terminates as a result of forming a continuous film of non-volatile copper fluoride (CuF) residue over the copper layer on the substrate. The residue isolates the remaining material layer of copper from the etchant gas, and the etchback process stops.
Therefore, there is a need in the art for an improved method of planarizing a copper interconnect structure during fabrication of the IC devices.
SUMMARY OF THE INVENTION
The present invention is a method of planarizing a copper interconnect structure using an atomic layer removal (ALR) technique to planarize a copper (Cu) layer. In one embodiment, the ALR process performs a plurality of cycles, each cycle having a period of exposing a layer of copper to a gas to form a layer of copper fluoride (CuF) on the copper layer and a period of removing the layer of copper fluoride.
The ALR process is repeated until a barrier layer beneath the copper layer is exposed. Then the barrier layer is etched to expose a layer of a dielectric material. The copper interconnect structure is now planarized such that a surface of the remaining copper layer is substantially coplanar with a surface of the layer of the dielectric material (i.e., IMD).


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